GD54 Search Results

RRUS 32

Abstract: CL-GD542X CL-GD543X CL-GD5452 CL-GD5453 bitblt GD54 vl-bus RRUS
Contextual Info: • CIRRUS LOGIC ElBbfc^ DGOMTbM E4T H C I R CL-GD5452/GD5453 Preliminary Product Bulletin FEATURES ■ Two-chip multiplexer-less, VRAM-based graphics accelerator ■ Resolutions supported: High-Resolution True Color Graphics Accelerator — 1280 x 1024 x 24 bits per pixel non-interlaced

CL-GD5465

Abstract: RD5106 vga to pal video convertor ic planar YUV display input 160x64 gd5465 D147 Crystal Oscillator 8574t 5FDT cirrus logic cl-gd
Contextual Info: . CL-GD5465 CIRRUS LOGIC • Preliminary Data Book FEATURES • 64-bit graphics engine with integrated 3D game acceleration — — — — — — — — — — — — — — — Perspective textures mapping FilterJet fast bilinear filtering Lit, copy, decal, and blend textures

Contextual Info: GD54/74LS195A 4-BIT PARALLEL ACCESS SHIFT REGISTERS Features • • • • • • • Synchronous parallel load Positive-edge-triggered clocking Parallel inputs and outputs from each flip-flop Direct overriding clear J and K inputs to first stage Complementary outputs from last stage

Contextual Info: GD54/74LS164 8-BIT PARALLEL OUTPUT SERIAL SHIFT REGISTER Feature • • • Pin Configuration Gated Enable/Disable Serial Inputs Fully Buffered Clock and Serial Inputs Asynchronous Clear OUTPUTS Vcc Oh 14 13 12 11 10 Qh Qg Qf Qe CLEAR I Qf Qe CLEAR CLOCK

Contextual Info: GD54/74HC165, GD54/74HCT165 8-BIT PARALLEL-IN/SERIAL-OUT SHIFT REGISTER General Description Pin Configuration These devices are identical in pinout to the 5 4 /74L S 16 5 . This circuit is an 8-bit, parallel-input to serial-output shift register with complementary

Contextual Info: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which performs the logic INVERT function. Each in­ put has hysteresis which increases the noise im­ munity and transforms a slowly changing input signal

Contextual Info: GD54/74HCU04 HEX UNBUFFERED INVERTERS General Description These devices are identical in pinout to the 5 4 /7 4 LS04. They contain six independent unbuffered in­ verters. These inverters are well suited for use as oscillators, pulse shapers and in many other applica­

74HC74

Abstract: 74hct74 74LS74 pinout 74HC74 pin configuration 74hc74 pin diagram TTL 74hc74 74ls74 timing setup hold Current 74HCT74 QQ042 000M2AA
Contextual Info: GD54/74HC74, GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR G e n era l D escrip tio n These devices are identical in pinout to the 5 4 /7 4 L S 7 4 . They consist of two D-type flip-flops with individual preset, clear, and clock inputs. Infor­ Pin C o n fig u ra tio n

Contextual Info: GD54/74LS145 BCD-TO-DECIMAL DECODER/DRIVER Features Pin Configuration • Full Decoding of Input Logic • 80-m A Sink-Current Capability • All Outputs Are Off for Invalid BCD Input Con­ ditions • Low Power Dissipation of ’L S 1 4 5 .3 5 mW Typical

Contextual Info: GD54/74HC283, GD54/74HCT283 4-BIT BINARY FULL ADDER WITH FAST CARRY General Description These d evices are identical in pinout to Pin Configuration the 5 4 /7 4 L S 2 8 3 . This full ad d er perform s the addition of tw o 4-b it binary num bers with internal carry

74HCT192

Contextual Info: GD54/74HC192, GD54/74HCT192 SYNCHRONOUS DECADE UP/DOWN COUNTER WITH A CLEAR & DUAL CLOCKS General Description Pin Configuration These devices are identical in pinout to the 5 4 /7 4 L S 1 92. This decade counter has two separate clock inputs; an up count input and a down

74LS193 function table

Contextual Info: GD54/74LS193 SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS.BINARY WITH CLEAR Feature Pin Configuration • Cascading Circuitry Provided Internally • Synchronous Operation • Individual Preset to Each Flip-Flop • Fully Independent Clear Input INPUTS INPUTS Vcc

Contextual Info: GD54/74LS05 HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS D escrip tion This device contains six idenpendent inverts. It perform s the Boolean function Y = A. T he open col­ lector outputs require pull-up resistor to perform cor­ rectly. O pen -co llector d evices are often used to

Contextual Info: GD54/74S158 QUADRUPLE 2-T0-1-LINE DATA SELECTORS/MULTIPLEXERS INVERTED DATA OUTPUTS Features Pin Configuration • Buffered Inputs and Outputs • Converted outputs provided. INPUTS R R R R 12 ” R FI o 1 !> Applications • Expand Any Data Input Point

Contextual Info: GD54/74LS26 QUAD 2-INPUT NAND GATES WITH HIGH VOLTAGE OPEN-COLLECTOR OUTPUTS Features Pin C onfiguration • Usable in AND-Tie connection • High Output Voltage 15V Vcc 4B 4A 4Y 3B 3A D escription This device contains four independent gates each of which performs the logic NAND function. The

Contextual Info: GD54/74S02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES Description Pin Configuration This device contains four independent 2-input NOR gates. It performs the Boolean functions Y = A B or Y = A + B in positive logic. 3B n fi fi r fi r <tU l<£- Function Table OUTPUT

Contextual Info: GD54/74S86 QUADRUPLE 2-INPUT EXCULSIVE-OR GATES Description Pin Configuration This d evice contains four independent 2-input Exclusive-O R gates. It perform s the Boolean func­ tions Y = A B = A B + A B inpositive logic. 14 4B 4A 13 12 4Y 11 3B 3A 3Y 10

74LS08 pin configuration

Abstract: 74LS08 function table
Contextual Info: GD54/74LS08 QUADRUPLE 2-INPUT POSITIVE AND GATES Description Pin Configuration This device contains four independent 2-input AND gates. It performs the Boolean functions Y = A B or Y = A + B in positive logic. Vcc 4B 4A 4'i 3B 3A 3Y 14 13 12 1 10 9 8 i - Function Table each gate

Contextual Info: GD54/74S163A SYNCHRONOUS 4-BIT COUNTER: BINARY. SYNCHRONOUS CLEAR Feature Pin Configuration • • • • • • Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs

Contextual Info: GD54/74HC191, GD54/74HCT191 SYNCHRONOUS 4-BIT BINARY UP-DOWN COUNTER WITH MODE CONTROL General Description These d e vices are identical in pinout to the 5 4 /7 4 L S 1 9 1 . This synch ron ous, reversible, 4-B it binary up/down counter can be preset by applying the

Contextual Info: GD54/74LS367A HEX BUS DRIVERS WITH 3-STATE OUTPUTS Feature • 3-State Outputs Drive Bus Line or Buffer Memory Address Registers • Choice of True or Inverting Outputs Pin Configuration Vcc G2 6A 6Y 5A 5Y 4A 4Y Description These hex buffers and line drivers are designed

Contextual Info: Technical D a ta _ CD54/74AC373, CD54/74AC533 CD54/74ACT373, GD54/74ACT533 D O -D t -D 2 -0 3 - Octal Transparent Latch, 3-State 373 533 Q1 si — oz Q2 C D 54/74AC /A CT373 - Non-Inverting C D 54/74AC /A CT533 - Inverting

LG 631 TV LG power supply

Abstract: lg crt tv motherboard circuit diagram Cirrus CL-GD5428 ihp 1c manual cl-gd5420 lg flat crt tv electronic diagram D5426 LG 631 TV LG lg flat screen crt tv electronic diagram 5420 bios
Contextual Info: CL-GD542X Preliminary Data Book 'CIRRUS LOGIC True Color VGA Family CL-GD5429 - Memory-Mapped I/O VGA GUI FEATURES • 32-bit GUI acceleration CL-GD5426/’28/’29 Accelerator with Local Bus — BitBLT (Bit block transfer) engine — Color expansion for 8- or 16-bit pixels

3d graphics

Abstract: "3d graphics" z-buffer CL-GD5464
Contextual Info: CL-GD546X CIRRUS LOGIC 8 A dvance P roduct B ulletin FEATURES High-Performance VisualMedla Accelerators • 64-blt graphics engine with integrated 3D game acceleration CL-GD5464 CL-GD5462 (2D) CL-GD5464 (3D) CL-GD5465 (AGP) - Perspective textures mapping