GAZELLE Search Results

Contextual Info: G A 2 2 V P 10 High-Perform ance Logic Device G allium Arsenide g a z e lle Features G eneral Description Gazelle’s GA22VP10 is a TTL-compatible, high-performance logic device HPLD . The GA22VP10 is functionally equivalent to the popular GA22V10, but with the improved Output Logic Macrocells (OLMs) offering

GA22V10

Abstract: Federal fuse switch Gazelle Gazelle Microcircuits 80386 microprocessor pin out diagram hpld
Contextual Info: GA22VP10 H ig h -P erfo rm an ce Logic D evice G allium A rsen id e gazelle F e a tu re s G en e ra l D esc rip tio n Gazelle’s GA22VP10 is a TTL-compatible, high-performance logic device HPLD . TheGA22VP10 is functionally equivalentto the popular GA22V10,

Contextual Info: '.fit PRELIMINARY DEVICE SPECIFICATION MULTI-PHASE CLOCK GENERATOR/LOW-SKEW TTL CLOCK BUFFER SC1110 I FEATURES GENERAL DESCRIPTION • Pin-for-pin replacement for Triquint/Gazelle GA1110E • “Zero-propagation delay” clock buffer provides ±250 ps typ , ±1 ns (max) input to output delay

Contextual Info: GA23SV8/GA23S8 High-Perform ance Logic Device Gallium Arsenide gazelle _ G eneral Description Features Gazelle’s GA23SV8/GA23S8 are TTL-compatible high-performance logic sequencers. Based on the fam iliar programmable array logic architecture, they provide highest performance and

Contextual Info: G A 22VP10-10 H igh*Perform ance Logic Device G allium Arsenide g a z e l l e - Features G eneral Description Gazelle’s GA22VP10 is a TTL-compatible, high-performance logic device HPLD . The GA22VP10 is functionally equivalent to the popular GA22V10,

GA1210

Abstract: ga22vp10-7 gazelle
Contextual Info: GA1210 r a Low -Skew TTL Clock Doubler Tw o-Phase Clock G enerator J gazelle G eneral Description Features Gazelle’s G/^1210 is a low-skew TTL-level clock doubler chip. It producesm ul^eclockoutputs, at precisely 2Xtheinputfrequency, which are all p^ise-aligned to a periodic clock input signal. The

ats 2300

Abstract: A23S8
Contextual Info: GA23SV8/GA23S8 gazelle High-Perform ance Logic Device Gallium Arsenide _ Features G eneral Description G azelle’s GA23SV8/GA23S8 are TTL-compatible high-perform­ ance logic sequencers. Based on the fam iliar programmable array logic architecture, they provide highest performance and

gazelle microcircuits

Contextual Info: NOM 2 i 1990 GA1210E Low-Skew TTL Clock Doubler Two-Phase Clock G enerator gazelle General Description Features Gazelle’s GA121OE is a low-skew TTL-level clock doubler chip. It produces multiple clock outputs, at precisely 2X the input frequency, which are all phase-aligned to a periodic clock input signal. The

Contextual Info: GA11 1 0 M ulti-Phase Clock G enerator Low -Skew TTL Clock Buffer r gazelle Features G eneral Description Gazelle’s GA1110 is a low-skew TTL-level clock buffer chip with : multi-phase clock generation. It produces multiple clock outputs which are phase and frequency synchronized to a periodic clock

Contextual Info: G A Z E LL E M I C R O C I R C U I T S INC S'ÎE ]> • 3fl3bOB5 OOOOO'îl ô W Ê G k l T^i-OD r m Q A 121OE Low-Skew TTL Clock Doubler Two-Phase Clock Generator J è gazelle General Description Features Gazelle's GA1210E is a low-skew TTL-level clock doubler chip. It

GA22V10

Contextual Info: G A22V10 g a ze lle High-Perform ance Logic Device Gallium Arsenide _ G eneral Description Features Gazelle’s GA22V10 is a TTL-compatible, high-performance logic device HPLD . For existing users of PLDs, it provides a pincompatible path to upgrade system performance. For designers

18p8

Abstract: 18v8 23S8
Contextual Info: _ * Gl GA23SV8/GA23S8 gazelle H ig h -P erfo rm an ce L o g ic D e v ice G alliu m A rse n id e _ G e n e ra l D e scrip tio n G azelle’s GA23SV8/GA23S8 are TTL-compatible high-perform­ ance logic sequencers. Based on the fam iliar programmable

SC1110

Contextual Info: PRELIMINARY DEVICE SPECIFICATION LOW-SKEW TTL CLOCK DOUBLER/TWO-PHASE CLOCK GENERATOR SC1210 FEATURES GENERAL DESCRIPTION • Pin-for-pin replacement for Triquint/Gazelle GA1210E AMCC’s SC1210 is a low-skew TTL-level clock doubler chip providing high-speed clock generation and routing.

Contextual Info: G azelle M icrocircuits, Inc. PLD Product Sum m ary gazelle SPEED GA22V10 GA22VP10 GA23S8 GA23SV8 Notes: * MHz (ns) PART NUMBER (mA) 'cc PRODUCT TERMS REGISTERS DEDICATED INPUTS I/O PIN COUNT 200 220 124 10 12 10 24/28 DIP/CLCC 111 200 220 124 10 12 10 24/28

Contextual Info: G A Z E L L E M ICR O CIR C U ITS INC 14E 0 § 3 â 3 t,[m 0000033 5 | GA23SV8/GA23S8 g a z e lle High-Perform ance Logic D evice G allium A rsenide _ G eneral D escription Gazelle’s GA23SV8/GA23S8 are TTL-compatible high-perform­ ance logic sequencers. Based on the familiar programmable

Contextual Info: G A 22VP10-7 High*Perform ance Logic Device Gallium Arsenide gazelle - Features G eneral Description Gazelle’s GA22VP10 is a TTL-compatible, high-performance logic device HPLD . TheGA22VP10 isf unctionally equivalent to the popular GA22V10,

GA22V10

Abstract: ga22vp10-7 gazelle
Contextual Info: lTM HOT ROD ;y MD im High-Speed S erial Link G allium A rsenide g azelle G eneral D escription Features The HOT ROD transmitter and receiver pair from Gazelle is a 100 Mbit/sec to 1 Gbit/sec point-to-point data communications chipset. It is ideal for use in high-performance systems where data

Contextual Info: GA1110E r « M ulti-Phase Clock G enerator Low-Skew TTL Clock Buffer J g a z e lle G eneral Description Features Gazelle’s GA1110E is a low-skew TTL-level clock buffer chip with multi-phase clock generation. It produces multiple clock outputs which are phase and frequency synchronized to a periodic clock

Contextual Info: Integrated Circuit Systems, Inc. AV9172 Low Skew Output Buffer General Description Features The AV9172 is designed to generate low skew clocks for clock distribution in high-performance PCs and workstations. It uses phase-locked loop technology to align the phase and

AV9172-07

Abstract: marking 2x AV9172 AV9172-01 AV9172-03 GA1210
Contextual Info: Integrated Circuit Systems, Inc. AV9172 Low Skew Output Buffer General Description Features The AV9172 is designed to generate low skew clocks for clock distribution in high-performance PCs and workstations. It uses phase-locked loop technology to align the phase and

Contextual Info: IBM2520L8767 Preliminary ATM Resource Manager Features other uses DRAM devices. A single array of memory can be used in systems whose sus­ tained full-duplex total bandwidth requirement is less than 102Mb/s. • Optimized for server applications. • Configurable for sustained performance of up to

Contextual Info: AV9172 Integrated Circuit Systems, Inc. Advance Information Low Skew Output Buffer General Description Features The AV9172 is designed to generate low skew clocks for clock distribution in high-performance PCs and workstations. It uses phase-locked loop technology to align the phase and frequency

PR2000

Abstract: PR3000A MIPS R3000A R2000 mips processor
Contextual Info: PERFORMANCE INTEGRATED MIPS MODULE PIMM” FEATURES: • • bus snooper to assist In maintaining cache coherency in multiprocessor systems Single VLSI multichip module contains: • PR3000A CPU • PR3010A FPA ■ P4C92815 x4 Bicameral SCRAM contains: • 32 KBytes each of address latched

resistive touch screen controller

Abstract: touch screen BLOCK DIAGRAM OF 4 wire resistive TOUCH screen MK712SLF 17 inch touch screen monitor BLOCK DIAGRAM OF TOUCH PLATE touch screen controller MK712 MK712RLF MK712RLFTR
Contextual Info: DATASHEET MK712 TOUCH SCREEN CONTROLLER Description Features The MK712 Touch Screen Controller IC provides all the screen drive, A to D converter and control circuits to easily interface to 4-wire analog resistive touch screens. • Packaged in 28-pin SSOP 150 mil or 28-pin SOIC (300