G681 Search Results

Contextual Info: G680/G681 Global Mixed-mode Technology Microprocessor Reset IC Features „ „ „ „ „ „ „ „ General Description ±2.5% Voltage Threshold Accuracy Independently Adjustable High- and LowVoltage Thresholds The G680/G681 are microprocessor µP supervisory

G680LT1

Abstract: CG680
Contextual Info: G680/G681 Global Mixed-mode Technology Inc. Microprocessor Reset IC Features „ „ „ „ „ „ „ „ General Description High ±2% Voltage Threshold Accuracy Independently Adjustable High- and LowVoltage Thresholds The G680/G681 are microprocessor µP supervisory

G680LT1

Abstract: G680 G680HT1 G681 G681LT1
Contextual Info: G680/G681 Global Mixed-mode Technology Inc. Microprocessor Reset IC Features General Description „High ±2% Voltage Threshold Accuracy „Independently Adjustable High- and Low- The G680/G681 are microprocessor µP supervisory circuits used to monitor the power supplies in µP and

G680LT1

Abstract: G680 G680HT1 G681 G681LT1 G680H
Contextual Info: G680/G681 Global Mixed-mode Technology Inc. Microprocessor Reset IC Features General Description „High ±2% Voltage Threshold Accuracy „Independently Adjustable High- and Low- The G680/G681 are microprocessor µP supervisory circuits used to monitor the power supplies in µP and

G680LT1Uf

Abstract: G680LT1U G680LT1 sot-23-5 marking code G681 G680 UPS design Guide A1 MARKING SOT-23-5 reset IC sot23
Contextual Info: G680/G681 Global Mixed-mode Technology Inc. Microprocessor Reset IC Features „ „ „ „ „ „ „ „ General Description High ±2% Voltage Threshold Accuracy Independently Adjustable High- and LowVoltage Thresholds The G680/G681 are microprocessor µP supervisory

Contextual Info: Package Outlines M O LD ED D U A L IN-LINE P A C K A G E S PC-024 PC-024 Slim A ^ A /S A A A A A A A ft 24 ^ .206 “ l> D J. 12 'U U U U U U U U U U iJ iu j1 —•! - 4 0 6 MM. SEATING .180 •140 .226 ¿15 :=lw«mF4 j/c=^ s ^EfwvpwH1/' sHI 2 4-S MS—\

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT IDT7015S/L STATIC RAM I n t e g r a t e d D e v iz e T e c h n o lo g y , l i e . FEATURES: • True Dual-Ported m em ory cells which allow sim ulta­ neous reads of the sam e m em ory location • H igh-speed access — M ilitary: 20/25/35ns max.

Contextual Info: HIGH-SPEED 36K 4K x 9-BIT SYNCHRONOUS DUAL-PORT RAM PRELIMINARY IDT70914S Integ ra te d D evice Technology, Inc. FEATURES: DESCRIPTION: • High-speed clock-to-data output times — Military: 20/25ns (max.) — Commercial: 15/20/25ns (max.) • Low-power operation

Contextual Info: dt | ; HIGH-SPEED 16Kx 8 DUAL-PORT STATIC RAM IDT7006S/L In te g ra te d De v ic e T e ch n o lo g y, Inc. FEATURES: • • • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location • H igh-speed access — M ilitary: 20/25/35/55/70ns max.)

Contextual Info: HIGH-SPEED 16Kx 8 DUAL-PORT STATIC RAM IDT7006S/L Integrated Device Technology, Inc. M/S = L for BUSY input on Slave • Interrupt Flag • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

Contextual Info: |9 | N a HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM w Éy IDT7005S/L Integrated Device Technology, Inc. • Interrupt Flag • On-chlp port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM ydt IDT7015S/L Integrated De^/ice Technology, Inc. FEATURES: • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location • H igh-speed access — M ilitary: 20/25/35ns max.)

Contextual Info: bbE D INTEGRATE» DEVICE B 4ÔSS771 0015534 bMT « I D T CMOS SyncFlFO 256 X 18, 512 X 18,1024 x 18, 2048 x 18 and 4 096x18 ID T 7 2 2 0 5 L B ID T 7 2 2 1 5 L B ID T 7 2 2 2 5 L B ID T 7 2 2 3 5 L B ID T 7 2 2 4 5 L B Integrated Device Technology, Inc.

Contextual Info: IDT72261 IDT72271 CMOS SUPERSYNC FIFO 16,384x9, 32,768x9 FEATURES: DESCRIPTION: • • • • • • The IDT72261/72271 are monolithic, CMOS, high capac­ ity, high speed, low power first-in, first-out FIFO memories with clocked read and write controls. These FIFOs are

Contextual Info: HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT STATIC RAM PRELIMINARY IDT70914S In tegrated D e v ic e T e c h n o lo g y , Inc. FEATURES: DESCRIPTION: • H igh-speed clock-to-data output tim es — Military: 20/25ns max. — C om m ercial: 15/20/25ns (max.) • Low -power operation

Contextual Info: PRELIMINARY IDT72V261 IDT72V271 CMOS SUPERSYNC FIFO 16,384x9, 32,768x9 FEATURES: • 3.3Volt operation saves 60 percent of power compared to the functionally compatible 5 Volt 72V261/72V271 family • 16,384 x 9-bit storage capacity IDT72261 • 32,768 x 9-bit storage capacity (IDT72271)

Contextual Info: HIGH-SPEED 8K x 9 DUAL-PORT M J IDT7015S/L STATIC RAM Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simulta­ neous reads of the same memory location • High-speed access — Military: 20/25/35ns max. — Commercial: 12/15/17/20/25/35ns (max.)

Contextual Info: HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L I n t e g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: more using the M aster/Slave select when cascading more than one d evice • M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave

Contextual Info: HIGH-SPEED 1 6 K X 9 DUAL-PORT STATIC RAM ID T 7 0 1 6 S /L Features using the Master/Slave select when cascading more than * True Dual-Ported memory cells which allow sim ultaneous one d e v i c e _ reads of the sam e memory location M/S = V ih for B U S Y output flag on Master

Contextual Info: HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM IDT7005S/L In te g ra te d D e v ic e T ec h nology, In c . FEATURES: • Interrupt Flag • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port

A12L

Abstract: IDT7005 IDT7005L IDT7005S
Contextual Info: IDT7005S/L HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 20/25/35/55/70ns max. – Industrial: 35/55ns (max.) – Commercial:15/17/20/25/35/55ns (max.)

RUB25

Abstract: IDT7133SA7LA
Contextual Info: INTEGRATED 3ÛE DEVICE D • 4Û25771 DGQbbS7 1 ■ IDT PRELIMINARY IDT7133SA7LA IDT7143SA/LA CMOS DUAL-PORT RAMS 3 2 K 2 Kx 16-BIT Integrated Device Technology, Inc. RAMs. The IDT7133 is designed to be used as a stand-alone 16-bit dual-port RAM or as a "MASTER" dual-port RAM

LF 3.3vOLT

Contextual Info: PRELIMINARY IDT72V255 IDT72V265 3.3 VOLT CMOS SUPERSYN C FIFO 8,192x18,16,384x18 Integrated Device Technology, Inc. • Output enable puts data outputs into high impedance • High-performance submicron CMOS technology • Industrial temperature range -40°C to +85°C is avail­

02-Dl

Abstract: 72235 PGA 56C315 43536
Contextual Info: CMOS SyncFIFO 256 x 18, 512 x 18,1024 x 18, 2048 x 18 and 4096 x 18 FEATURES: • • • • • • • • • • • • • • • • • 256 x 18-bit organization array 72205LB 512 x 18-bit organization array (72215LB) 1024 x 18-bit organization array (72225LB)