FZ 9011 V Search Results

Contextual Info: QL4016 QuickRAM Data Sheet • • • • • • 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights Advanced I/O Capabilities • Interfaces with both 3.3 V and 5.0 V devices High Performance & High Density

Contextual Info: QL4009 QuickRAM Data Sheet • • • • • • 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights Advanced I/O Capabilities • Interfaces with both 3.3 V and 5.0 V devices High Performance & High Density

Contextual Info: QL4058 QuickRAM Data Sheet • • • • • • 58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights Advanced I/O Capabilities • Interfaces with both 3.3 V and 5.0 V devices High Performance & High Density

PQ208

Abstract: PQ240 QL4058 QL4058-1PB456C QL4058-1PQ208C QL4058-1PQ240C aldec g2
Contextual Info: QL4058 QuickRAM Data Sheet • • • • • • 58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights Advanced I/O Capabilities • Interfaces with both 3.3 V and 5.0 V devices High Performance & High Density

CQFP 240

Contextual Info: QL4090 QuickRAM Data Sheet • • • • • • 90,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights Advanced I/O Capabilities • Interfaces with 3.3 V and 5.0 V devices High Performance & High Density • 90,000 Usable PLD Gates with 316 I/Os

TMS320P14

Abstract: TMS320LC15
Contextual Info: TMS320C1X DIGITAL SIGNAL PROCESSORS JA N U A R Y 1987 — R E V IS E D J U L Y 1991 • Performance Up to 8.77 MIPs * Commercial and Military Versions Available • All TMS320C1x Devices are Object Code Compatible * Operating Free-Air Temperature . . . 0°C to 70°C

Contextual Info: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights Flexible Programmable Logic • 0.18 µm, six layer metal CMOS process • 1.8 V core voltage, 1.8/2.5/3.3 V drive

Contextual Info: QL5030 QuickPCI Data Sheet • • • • • • 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights Programmable Logic • 24 K system gates/266 logic cells High Performance PCI Controller • 9,216 RAM bits and 71 I/O pins

Contextual Info: QL5130 QuickPCI Data Sheet • • • • • • 33 MHz/32-Bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller Programmable Logic • 57 K system gates/619 logic cells • 13,824 RAM bits, up to 157 I/O pins

Contextual Info: QL5130 QuickPCI Data Sheet • • • • • • 33 MHz/32-Bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller Programmable Logic • 57 K system gates/619 logic cells • 13,824 RAM bits, up to 157 I/O pins

Contextual Info: QuickRAM Family Data Sheet • • • • • • QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights High Performance & High Density Up to 316 I/O Pins • Up to 308 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for

Contextual Info: QuickRAM Family Data Sheet • • • • • • QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights High Performance & High Density Up to 316 I/O Pins • Up to 308 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for

aldec g2

Contextual Info: Military QuickRAM Family Data Sheet • • • • • • Up to 90,000 Usable PLD Gates QuickRAM Combining Performance, Density and Embedded RAM Device Highlights High Performance & High Density • Up to 90,000 usable PLD gates with up to 316 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths,

Contextual Info: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights  20 quad clock networks per device Flexible Programmable Logic  4 quad clock networks per quadrant

Contextual Info: Eclipse-E Family Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Flexible Programmable Logic • 0.18 µm six layer metal CMOS process • 1.8/2.5/3.3 V drive capable I/O • Up to 1536 logic cells • Up to 4,002 flip-flops

Contextual Info: QuickLogic PolarPro Device Data Sheet — QL1P600 and QL1P1000 •••••• Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights  80 quad clock networks per device Low Power Programmable Logic

ql1p1

Abstract: QL1P600 BGA 256 PACKAGE power dissipation
Contextual Info: QuickLogic PolarPro Device Data Sheet — QL1P600 and QL1P1000 •••••• Combining Low Power, Performance, Density, and Embedded RAM • Quadrant-based segmentable clock networks Device Highlights Low Power Programmable Logic • As low as 25 µA

ql1p100

Contextual Info: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM Device Highlights • Quadrant-based segmentable clock networks  20 quad clock networks per device Flexible Programmable Logic  4 quad clock networks per quadrant

Contextual Info: QuickRAM Family Data Sheet • • • • • • Up to 90,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM Device Highlights High Performance & High Density Up to 316 I/O Pins • Up to 308 bi-directional input/output pins,

ECU schematic diagram

Contextual Info: QL6250E Eclipse-E Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine global clock networks: Flexible Programmable Logic  One dedicated • 0.18 µm six layer metal CMOS process

Appnote60

Contextual Info: QL6325E Eclipse-E Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine global clock networks: Flexible Programmable Logic  One dedicated • 0.18 µm six layer metal CMOS process

Contextual Info: QL6250E Eclipse-E Data Sheet •••••• FPGA Combining Performance, Density, and Embedded RAM Device Highlights Advanced Clock Network • Nine global clock networks: Flexible Programmable Logic  One dedicated • 0.18 µm six layer metal CMOS process

Contextual Info: QuickLogic PolarPro Data Sheet • • • • • • Combining Low Power, Performance, Density, and Embedded RAM Device Highlights • Quadrant-based segmentable clock networks  20 quad clock networks per device Flexible Programmable Logic  4 quad clock networks per quadrant

Contextual Info: QL904M QuickMIPS Data Sheet •••••• QuickMIPS Embedded Standard Product ESP Family Device Highlights Two Serial Ports • One with modem control signals CPU Core • One with IRDA-compliant signals • 32-bit MIPS 4Kc processor runs up to 233 MHz