FPLA APPLICATIONS Search Results

Contextual Info: INTERNATIONAL CMOS TECHNOLOGY, INC. PEEL253 CMOS Programmable Electrically Erasable Logic Device Features • ADVANCED CMOS EEPROM TECHNOLOGY ■ FPLA ARCHITECTURE ■ COMPATIBLE PERFORMANCE — tpD = 30ns max, to E = 30ns max SUPERSET REPLACEMENT FOR PLS153

lt 8224

Abstract: lt 8232 lt 8227 lt 8239 LT 8195 lt 8225 LT 8216 fn521 lt 8220 ep 8212
Contextual Info: Specifications GAL6002 GAL6002 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay

lt 8232

Abstract: LT 8233 lt 8217 LT 8209 LT 8223 lt 8219 GAL6002 GAL6002B-15LJ GAL6002B-15LP R/diode lt 8232
Contextual Info: Specifications GAL6002 GAL6002 High Performance E2CMOS FPLA Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay

GAL6001

Abstract: GAL6001B-30LJ GAL6001B-30LP 8178
Contextual Info: Specifications GAL6001 GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay

GAL6001

Abstract: GAL6001B-30LJ GAL6001B-30LP
Contextual Info: Specifications GAL6001 GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay

273-12/PEELT273-15

Abstract: PEEL22CV10ZP-25
Contextual Info: Preliminary Information INC. PEEL 273-12/PEELT273-15 CMOS Programmable Electrically Erasable Logic Device Features • ADVANCED CM OS EEPROM TECHNOLOGY ■ FPLA ARCHITECTURE ■ LOW POW ER CONSUMPTION ■ SUPERSET REPLACEM ENT FOR PLS173 — — — —

Contextual Info: Lattice GAL6001B High Performance E2CMOS FPLA Generic Array Logic •■■■ FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E’CMOS* TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Max. Clock to Output Delay

ta 8221 H

Abstract: GAL6001 e2cmos technology GAL6001B-30LJ GAL6001B-30LP
Contextual Info: GAL6001 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs

lt 8232

Abstract: LT 8216 LT 8215 LT 8209 lt 8227 lt 8221 lt 8225 lt 8239 lt 8219 lt 8224
Contextual Info: Specifications GAL6002 GAL6002 High Performance E2CMOS FPLA Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES • HIGH PERFORMANCE E CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay

Contextual Info: Specifications GAL6001 GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay

signetics 82s100

Abstract: 82S100-I fpla 82S100 82S101 825100 82S100 programming 82S100/BXA
Contextual Info: s ig n o tic s BIPOLAR FIELD-PROGRAMMABLE LOGIC ARRAY 16X8X48 FPLA 82S101 (OPEN COLLECTOR) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 82S100 (TRI-STATE) O B JEC T IV E SPECIFICATION A P R IL 1975 825100 825101 DIGITAL 8000 SERIES TTL/MEMORY DESCRIPTION PIN CONFIGURATION

LT 8232

Abstract: LT 8215 lt 8225 LT 8224 lt 8220 lt 8228 lt 8239 LT 8229 LT 8233 lt 8227
Contextual Info: GAL6002 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram ICLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs

GAL6001

Abstract: GAL6001B-30LJ GAL6001B-30LP
Contextual Info: GAL6001 High Performance E2CMOS FPLA Generic Array Logic Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Maximum Clock to Output Delay — TTL Compatible 16mA Outputs

GAL6002

Abstract: MAX235 T-FLIP FLOPS maxim rs232 multiplexer
Contextual Info: GAL 6002: 4-to-1 RS232 Port Multiplexer Figure 1. TxD During Single Byte Transfer Introduction The GAL6002 is the most versatile 24-pin PLD available today. Its FPLA architecture offers buried macrocells, D/E registers, programmable clocks and dedicated input

8256 ap

Contextual Info: Lattice GAL6002B High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Max. Clock to Output Delay — TTL Compatible 16mA Outputs

GAL6002

Abstract: MAX235
Contextual Info: GAL 6002: 4-to-1 RS232 Port Multiplexer Figure 1. TxD During Single Byte Transfer Introduction The GAL6002 is the most versatile 24-pin PLD available today. Its FPLA architecture offers buried macrocells, D/E registers, programmable clocks and dedicated input

Contextual Info: Lattice GAL6001 High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 30ns Maximum Propagation Delay — 27MHz Maximum Frequency — 12ns Max. Clock to Output Delay — TTL Compatible 16mA Output«

PLS161

Abstract: PLS161N
Contextual Info: PLS161 Signetics Field-Programmable Logic Array 12 X 48 X 8 Signetics Programmable Logic Product Specification Application Specific Products • Series 24 DESCRIPTION FEATURES The PLS161 is a bipolar, Field-Programmable Logic Array (FPLA). The device utilizes the standard AND/OR/lnvert ar­

Contextual Info: GAL6001 Lattice High Performance E2CMOS FPLA Generic Array Logic Semiconductor • ■ ■ ■ Corporation FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E2CMOS TECHNOLOG Y — 30ns Maxim um Propagation Delay — 27MHz Maxim um Frequency — 12ns Maxim um Clock to Output Delay

Contextual Info: 37E D INTERNATIONAL C M O S 4Ô40707 GOQGBTl T MICT Product Preview INTERNATIONAL CMOS TECHNOLOGY, INC. T—46—19-07 PEEL 273-15 CMOS Programmable Electrically Erasable Logic Device Features • ADVANCED CMOS EEPROM TECHNOLOGY ■ FPLA ARCHITECTURE SUPERSET REPLACEMENT FOR PLS173

V 7271 U

Abstract: IM5200 IVI5200 PT46 l3t1
Contextual Info: DOM^OIL IM5200 Field Programmable Logic Array FPLA GENERAL DESCRIPTION FEATURES • • • • • • • • • Avalanche Induced M igration (A IM ) Program m ability 4 8 Product Term s, 14 Inputs, 8 O utputs O u tp u t A ctive Level — High or Low

Contextual Info: GAL6002 Lattice High Performance E2CMOS FPLA Generic Array Logic ! Semiconductor I •■■ Corporation FUNCTIO N AL B LO C K DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOG Y — 15ns Maximum Propagation Delay — 75MHz Maximum Frequency — 6.5ns Maximum Clock to O utput Delay

Contextual Info: LAT T IC E S E M I C O N D U C T O R bflE D • 5 3 0 ^ 4 = ] DDDSTtiM 177 « L A T GAL6002 Lattice High Performance E2CMOS FPLA Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE EJCMOS* TECHNOLOGY — 15ns Maximum Propagation Delay

82S123 programming

Abstract: PJ 3139 prom 82S126 NCE8205 82s131 programming Signetics 2513 SIGNETICS prom ttl 512 CM340 82s129 programming Signetics 2608
Contextual Info: Ejgnotics ROM/PROM CONTENTS T TL PROM CONTENTS PAGE 2 T TL FPLA C O N T E N T S . PAGE 2 ECL PROM CONTENTS PAGE 3 SIGNETICS PROM R E L IA B IL IT Y PAGE 35 T TL ROM C O N T E N T S . PAGE 3 T T L ROM O R D ER IN G INFO