FOR64 Search Results

Contextual Info: AT28C1024 Features • • • • • • • • • • • Fast Read Access Time -120 ns Automatic Page Write Operation Internal Address and Data Latches for64 Words Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 10 ms maximum 1 to 64 Word Page Write Operation

hfdw

Contextual Info: _ ü 16/18Mbit 2Mx8/9 & 64/72Mbit (8Mx8/9) ConcurrentRDRAM Overview VDD GND BUSDATA[8] GND BUSDATA[7] (NC) BUSENABLE VDD BUSDATA[6] GND BUSDATA[5] VDDA RXCLK GNDA TXCLK VDD BUSDATA[4] GND BUSCTRL SIN VREF SOUT BUSDATA[3] GND BUSDATA[2] (NC)

msm16951

Abstract: CAT59C11 msm*16951 128x8 or gate 24 volt
Contextual Info: O K I semiconductor MSM 16951 1,024-B it SER IA L E2PROM FEATURES: • • • • • • • • • • • PIN CONFIGURATION CMOS Floating Gate Technology Single +5-volt supply Eight pin plastic package 64 x 16 or 128 x 8 user selectable serial memory

Contextual Info: FUJITSU M I C R O E L EC TR ON IC S FU JITSU 3 7 4 ^ 7 tiS DOQ4LSÖ DYNAMIC % IRAM CONTROLLER ADVANCE INFORMATION DESCRIPTION The Fujitsu MB1430 Dynamic RAM DRAM Controller Is a high-performance device that provides all control functions required to Implement and supervise a muitiple-DRAM memory. Major functions Include multiplexed address control, memory refresh, and

Contextual Info: Preliminary Information V fE X A R XR16C854 QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO H F DESCRIPTION The XR16C854 *1 854 is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554D/654 and ST68C554/654. The 854 is an enhanced UART with 128 byte

Contextual Info: fax id: 5214 CYPRESS CY7C008V/009V CY7C018V/019V PRELIMINARY 3.3V 64K/128K x 8/9 Dual-Port Static RAM Features Fully asynchronous operation Automatic power-down Expandable data bus to 16/18 bits or more using Mas­ ter/Slave chip select when using more than one device

Contextual Info: CMOS SyncFIFO 64x8, 256x8,512x8, 1024 x 8, 2048 x 8 and 4096 x 8 IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240 FEATURES: DESCRIPTION: • • • • • • • • • T he ID T 7 2 4 2 0 /7 2 2 0 0 /7 2 2 1 0 /7 2 2 2 0 /7 2 2 3 0 /7 2 2 4 0

90C31

Contextual Info: m ^7ifi52fl ooma?a 1 ? 'T - S 2 - 3 S - 4 £ WD90C31A High Performance Video Controller with Windows Accelerator WD90C31A WESTERN DIGITAL CORP 54E ]> • ^710220 001407*} 003 Hlil] TABLE OF CONTENTS T—5 2 - 3 3 - 4 5 Section Title Page , 1.0 INTRODUCTION

ILO75

Contextual Info: fax id: 5215 CYPRESS CY7C027V/028V CY7C037V/038V PRELIMINARY 3.3V 32K/64KX 16/18 Dual-Port Static RAM Features • Fully asynchronous operation • Automatic power-down • Expandable data bus to 32/36 bits or more using Mas­ ter/Slave chip select when using more than one device

2964B

Abstract: N2964BI N2964BN
Contextual Info: Signetics 29Ó4B Dynamic Memory Controller Product Specification Logic Products FEATURES • Operating Options — controls 16K or 64K DRAMs • 8-Bit Refresh Counter — refresh address generation, clear input, and selectable terminal count 128 or 256 output

NIC1000

Abstract: ST16C554 ST16C654 ST16C654CQ64 ST16C654DCQ64 ST68C554 NIC100
Contextual Info: V fE X A R ST16C654/654D QUAD UART WITH 64-BYTE FIFO AND INFRARED IrDA ENCODER/DECODER DESCRIPTION The ST16C654 *1 is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554 and ST68C554. The 654 is an enhanced UART with 64 byte FIFO’s, automatic

concurrent rdram

Abstract: RDRAM CONCURRENT es a 00112 concurrent rdram 72 mbit concurrent RDRAM 72 9 rambus concurrent rdram R64MC-50-600 SVP-32 rdram clock generator concurrent RDRAM 72
Contextual Info: Preliminary Information Concurrent RDRAM ® 16/18Mbit 2Mx8/9 & 64/72Mbit (8Mx8/9) RAMBUS Overview The 16/18/64/72-Mbit Concurrent Rambus DRAMs (RDRAM) are extremely high-speed CMOS DRAMs organized as 2M or 8M words by 8 or 9 bits. They are capable of bursting unlimited lengths of data at 1.67 ns

16C654DCQ64

Abstract: st16c6541
Contextual Info: ST16C654/654D QUAD UART WITH 64-BYTE FIFO AND INFRARED IrDA ENCODER/DECODER DESCRIPTION The ST16C654 *1 is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554 and ST68C554. The 654 is an enhanced UART with 64 byte FIFO’s, automatic