FLEX8000A Search Results

EPF8820

Contextual Info: Includes FLEX8000A FLE X 8000 OUUU Programmable Logic Device Family March 1995, ver. 6 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS programmable logic device family 2,500 to 16,000 usable gates 282 to 1,500 registers see Table 1

EPM7160 Transition

Abstract: 6402 uart 4 bit updown counter vhdl code EPM7064L-84 epf8282alc84-4 ep330 EPM7192 Date Code Formats EPM7160L-84 EPF81500ARI240-3 EPF81500ARI240
Contextual Info: Newsletter for Altera Customers ◆ Third Quarter ◆ August 1996 ClockLock & ClockBoost Circuitry for High-Density PLDs Altera is introducing two new options for high-density programmable logic devices PLDs . The ClockLock feature uses a phase-locked loop (PLL) to minimize

Contextual Info: FLEX 8000 Programmable Logic Device Family S e p te m b e r 1S9S» v e r. 9.11 Features. D ata S h e e t Low-cost, high-density, register-rich CMOS programmable logic device PLD family (see T;?bie 1) 2,500 to 16,000 usable gates 282 to 1,500 registers

Contextual Info: FLEX 8000 Programmable Logic Device Family M ay 1999» ver. 10 Features. Data Sheet Low-cost, high-density, register-rich CMOS programmable logic device PLD family (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers System-level features

pf815

Abstract: sim 300 v 703 p10n10
Contextual Info: F L E X 8000 Programmable Logic Device Family J a n u a r y 1 9 9 8 . v e r. 9 Features. D a ta S h e e t • ■ ■ ■ ■ Low -cost, high-density, register-rich CMOS p ro gram m able logic device PLD fam ily (see Table 1) 2,500 to 16,000 usable gates