FIELD RATE CONVERSION Search Results

SAA4991WP

Abstract: sMD .v05 dpcm IC Ensemble smd tr yc smd V05 transistor SMD .v05 UV 471 CLK32 QFP160
Contextual Info: INTEGRATED CIRCUITS DATA SHEET SAA4992H Field and line rate converter with noise reduction Product specification File under Integrated Circuits, IC02 2000 Feb 04 Philips Semiconductors Product specification Field and line rate converter with noise reduction

Contextual Info: TACHTR0L 2 Low-cost Digital Speed/ Rate Monitor Part Number Series T77220 Features & Advantages • Single-channel precision speed or rate monitoring. • Period mode measuring system. • Field adjustable normalization. • Five-digit auto-ranging .56" L.E.D.

ADM1491E

Abstract: ADM1490E ADM1491EBRMZ MA701
Contextual Info: 16 Mbps, ESD Protected, Full-Duplex RS-485 Transceivers ADM1490E/ADM1491E APPLICATIONS RS-485/RS-422 interfaces Industrial field networks High data rate motor control Multipoint data transmission systems Single-ended-to-differential signal conversion FUNCTIONAL BLOCK DIAGRAMS

LIE 300 X002

Abstract: TMC2208 TMC2301 Fairchild F8 example marking ca7
Contextual Info: www.fairchildsemi.com TMC2301 Image Resampling Sequencer 15, 18, 20 MHz Features Applications • Rotation, warping, panning, zooming, and compression of images in real time • 20 MHz clock rate • 4096 x 4096 image field addressing capability • User-selectable nearest-neighbor, bilinear interpolation,

specification of ldr

Abstract: TMC2208 TMC2301 marking code k9 DO 214 marking ca7
Contextual Info: www.fairchildsemi.com TMC2301 Image Resampling Sequencer 15, 18, 20 MHz Features Applications • Rotation, warping, panning, zooming, and compression of images in real time • 20 MHz clock rate • 4096 x 4096 image field addressing capability • User-selectable nearest-neighbor, bilinear interpolation,

esm 310 BP

Abstract: automatic change over switch circuit diagram TV 2 way splitter, circuit diagram TO-39, UVC SAA4991WP motion DETECTOR CIRCUIT DIAGRAM 2 way video splitter circuit diagram basic television block diagram color tv block diagram Digital clock MODULE CIRCUIT DIAGRAM
Contextual Info: APPLICATION NOTE Improved Picture Quality IPQ Module MK12 Version: 1.0 AN01017 Philips Semiconductors Improved Picture Quality (IPQ) Module MK12 Version: 1.0 Application Note AN01017 Abstract The Improved Picture Quality (IPQ) module MK12 is a high-end scan converter module providing field rate doubling and de-interlacing (conversion to progressive scan mode). The scan converter uses the ICs SAA4992

TIB82S105BC

Contextual Info: TIB82S105BC 16 x 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER WITH 3-STATE OUTPUTS OR PRESET SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995 • • • • • • N PACKAGE 50-MHz Clock Rate TOP VIEW Power-On Preset of All Flip-Flops CLK I7

TIB82S105BC

Abstract: TIB82S105BCFN TIB82S105BCN MS-011
Contextual Info: TIB82S105BC 16 x 48 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER WITH 3-STATE OUTPUTS OR PRESET SRPS025A – D2897, SEPTEMBER 1985 – REVISED NOVEMBER 1995 • • • • • • N PACKAGE 50-MHz Clock Rate TOP VIEW Power-On Preset of All Flip-Flops CLK I7

LC-15

Abstract: LC-40 ODW-621 ODW-631 fibre optic LED
Contextual Info: ODW-621 RS-232 to fibre optic link, point to point applications … … … … … … … … … … … … Field of application 2 Fibre Optic Link Retiming Data rate up to 250 kbit/s 9-position D-sub connector Redundant power supply inputs Status interface for fault indication

NMA-5109

Abstract: NMA-5110 NMA-5111 NMA-5112 NMA-5200 NMA-5250 NMA-5300 NMA-5107 NMA-5108
Contextual Info: l NMA 5100 SERIES HIGH POWER NOISE GENERATORS 100 HZ TO 18 GH Z RevE / 10.2007 DESCRIPTION The NMA 5100 Series Noise Generators are ideal for high power applications like jamming and bit error rate testing. They come in a rugged, SMA connectorized package for use in the lab or the field,

PCI 6601

Abstract: finisar gigabit traffic 133Mbits
Contextual Info: Application Note October 1996 PCI-Based Gbit/s Fibre Channel Adapter Using ORCA Series FPGAs Overview This application note describes the design of a PCIbased Fibre Channel Adapter that includes ORCA field-programmable gate arrays. This adapter connects a fibre-channel fabric operating at a bit rate of 1.0625 Gbits/s to a PCI bus. The

80C51

Abstract: "decompress compress"
Contextual Info: $33/,&$7,21 127 ,PSURYHG 3LFWXUH 4XDOLW\ ,34 0RGXOH 0. Version 1.0 $1 Philips Semiconductors ,PSURYHG 3LFWXUH 4XDOLW\ ,34 0RGXOH 0. Version 1.0 $SSOLFDWLRQ 1RWH $1 $EVWUDFW The Improved Picture Quality (IPQ module MK11 is a high-end scan converter module providing field rate doubling and de-interlacing (conversion to progressive scan mode). The scan converter uses the ICs SAA 4992

TS3 Philips

Contextual Info: Philips Semiconductors Preliminary specification Progressive scan-Zoom and Noise reduction IC PROZONIC SAA4990H FEATURES GENERAL DESCRIPTION • Progressive scan conversion (262.5 to 525 or 312.5 to 625 lines/field) The Progressive scan-Zoom and Noise reduction IC,

tv schematic diagram PHILIPS TV RECEIVER 347H

Abstract: CRT TCL-2027u COLOUR TV SCHEMATIC DIAGRAM TV 2 way splitter, circuit diagram Video sync splitter lm MK14-EM EM 235 setting 2 way video splitter circuit diagram hosiden motion DETECTOR CIRCUIT DIAGRAM SAA7118
Contextual Info: APPLICATION NOTE Scan conversion using the SAA4998 FALCONIC-EM Version 1 AN10233 Philips Semiconductors Scan conversion using the SAA4998 Version 1 (FALCONIC-EM) Application Note AN10233 Abstract This application note describes the scan converter module MK14-EM. 50 or 60 Hz video input signals are converted to progressive scan or 100.120 Hz (scan rate doubling, 2fH and 2fV). A software solution permits conversion from 50 Hz to 60 Hz or 75 Hz also, with the horizontal frequency being doubled (2fH).

bt.656 parallel to RGB 565

Abstract: VGA to Y PB PR scart vga
Contextual Info: CH7015 Chrontel Advance Information CH7015 SDTV / HDTV Encoder Features 1.0 GENERAL DESCRIPTION • VGA to SDTV conversion supporting graphics resolutions up to 1024x768 • Analog YPrPb output for HDTV • HDTV support for 480p, 576p, 720p, 1080i and 1080p

TMS320VC5509

Abstract: SPRU433A C5000 C5509 TMS320C55X
Contextual Info: Application Report SPRA786 - November 2001 Programming the TMS320VC5509 ADC Peripheral Rishi Bhattacharya C5000 DSP Software Applications ABSTRACT This application note demonstrates the procedure used to program the TMS320VC5509 ADC peripheral. Basic operation of the ADC consists of the ADC initialization and conversion

Contextual Info: Active Errata List • • • • • • • • • • • Timer 2 – Baud Rate Generator – No IT When TF2 is Set by Software Timer 2 – Baud Rate Generator – Long Start Time UART – RB8 Lost with JBC on SCON Register ADC – Interrupt During Idle Conversion

A01013

Abstract: T89C51CC02 CAN20A autobaud
Contextual Info: Active Errata List • Timer 2 Baud Rate Generator Mode – Long Start Time • UART – RB8 Lost with JBC on SCON Register • CAN – CANCONCH Harmless Corruption • ADC – Interrupt During Idle Conversion • Flash/EEPROM – First Read After Load Disturbed

SMPTE 1080p level a

Contextual Info: 0XOWL GEN GF9330 High Performance SDTV/HDTV Deinterlacer PRELIMINARY DATA SHEET DEVICE OVERVIEW • De-interlace, Pass-Through and Film Frame Rate Down Conversion modes of operation The GF9330 is a high performance VDSP engine that performs high quality de-interlacing of interlaced digital

HDMI to SDI converter chip

Abstract: hdmi SDI post-production equipment block diagram for video sdi to hdmi 1080p60 1080p60 video encoder Sigma Designs genesis video scaler HDMI Rx OSD scaler sdi gennum
Contextual Info: White Paper Enabling Improved Image Format Conversion with FPGAs FPGAs offer a competitive alternative to format-conversion ASSPs, which do not focus on the broadcast market. Altera’s video framework makes it easy to build cost-effective customizable format conversion functions in FPGAs

Contextual Info: Active Errata List • • • • • • • • • • Timer 2 – Baud Rate Generator – No IT When TF2 is Set by Software Timer 2 – Baud Rate Generator – Long Start Time UART – RB8 Lost with JBC on SCON Register ADC – Interrupt During Idle Conversion

Contextual Info: CS4952/53 A Cirrus Logic Company NTSC/PAL Digital Video Encoder Features Description • Simultaneous composite and S-video output The CS4952/3 provides full conversion from YCbCr or YUV digital video formats into NTSC & PAL Composite and Y/C S-video analog video. Input formats can be

crystal 3.579545MHZ

Abstract: SCAMP
Contextual Info: CS4952/3 A Cirrus Logic Company NTSC/PAL Digital Video Encoder Features • • • • • • • • • • • • • • Description The CS4952/3 provides full conversion from YCbCr or Simultaneous composite and S-video output YUV digital video formats into NTSC & PAL Composite

ce 65 s encoder

Abstract: tv to vga converter ic vga to composite convert
Contextual Info: F A I R C H I L D s e m ic o n d u c t o r w w w .fa irc h ild s e m i.c o m tm TMC2360 V ideo Output Processor V G A to N T S C /P A L .Features Description • Single-package graphics to video conversion • Multiple input formats _ 640x480 50/60 Hz, 800x600 50 Hz