FI 36MHZ Search Results

Contextual Info: SN820X Wi-Fi Network Controller Module Family Data Sheet Version 1.4 November 7, 2013 Note: SyChip, LLC reserves the right to make changes in specifications at any time and without notice. The information furnished in this data sheet is believed to be accurate and reliable. However, no responsibility is

Contextual Info: SN820X Wi-Fi Network Controller Module Family Data Sheet Version 2.2 February 28, 2014 Note: Murata Electronics N.A, Inc Murata reserves the right to make changes in specifications at any time and without notice. The information furnished in this data sheet is believed to be accurate and reliable. However, no

Contextual Info: SN820X Wi-Fi Network Controller Module Family Data Sheet Version 2.1 December 17, 2013 Note: Murata Electronics N.A, Inc Murata reserves the right to make changes in specifications at any time and without notice. The information furnished in this data sheet is believed to be accurate and reliable. However, no

74164 with ic PIN DIAGRAM

Abstract: IC 74164 LS164 ic 74ls164 AND SPECIFICATIONS pin diagram of ic 74164
Contextual Info: Signetics 7 4 1 6 4 , LS164 Shift Registers 8-Bit Serial-ln Parallel-Out Shift Register Product Specification Logic Products FEATURES • • • • Gated serial Data inputs Typical shift frequency of 36MHz Asynchronous Master Reset Fully buffered Clock and Data

41ti

Contextual Info: September 1999 PRELIMINARY ^Ék Micro Linear ML6426 High Bandwidth Triple Video Riterswith Buffered Outputsfor RGB or YU V G B IB U L DESCRIPTION FEATURES The ML6426 are a fam ily of triple video filters w ith buffered outputs. There are several versions of the

IC 74164

Abstract: 74164 with ic PIN DIAGRAM pin diagram of ic 74164 ic 74ls164 AND SPECIFICATIONS 74164 truth table and pin diagram of IC 74164 LS164 74164 shift register IC 74164 14 PIN DIAGRAM IC 74164 PIN DIAGRAM
Contextual Info: 74164, L S I6 4 Shift Registers Signetics 8-Bit Serial-ln Parallel-Out Shift Register Product Specification Logic Products FEATURES • • • • Gated serial Data inputs Typical shift frequency of 36MHz Asynchronous Master Reset Fully buffered Clock and Data

nt802

Contextual Info: NT802-051 d a t a t r o n ic s NT802-051 Token Ring Interface Module Features • • • • • • Designed to meet IEEE 802.5 Specification Integrates both transmit and receive channels into one module Supports both STP and UTP transmission Industrial standard SMD package

Contextual Info: w w w .fairchildsem i.com S E M I C O N D U C T O R tm RC6505 Differential IF Front-End Description • • • • • • • • • • The RC6505 incorporates IF gain stages, reference generators and a crystal oscillator on a single chip. The high input impedance enables direct interface to a SAW filter,

ISO 11898-5

Contextual Info: HI-5110 CAN Controller with Integrated Transceiver September 2010 GENERAL DESCRIPTION FEATURES The HI-5110 is a standalone Controller Area Network CAN controller with built in transceiver. The device provides a complete, integrated, cost-effective solution for

ISO 11898-1

Abstract: HI-5113 HI-3110 DS5110 ISO 11898-5 TTCAN
Contextual Info: HI-5110 CAN Controller with Integrated Transceiver September 2010 GENERAL DESCRIPTION FEATURES The HI-5110 is a standalone Controller Area Network CAN controller with built in transceiver. The device provides a complete, integrated, cost-effective solution for

ISO 11898-1

Contextual Info: HI-5110 CAN Controller with Integrated Transceiver February 2012 GENERAL DESCRIPTION FEATURES The HI-5110 is a standalone Controller Area Network CAN controller with built in transceiver. The device provides a complete, integrated, cost-effective solution for

tlc 5421

Abstract: ocs ctc tlc5411 723T HDC3
Contextual Info: n = J S G S -T H O M S O N S T L C 5411 2B1Q U INTERFACE DEVICE GENERAL FEATURES • SINGLE CHIP 2B1Q LINE CODE TRANS­ CEIVER . SUITABLE FOR BOTH ISDN AND PAIR GAIN APPLICATIONS ■ MEETS OR EXCEEDS ANSI U.S. AND ETSI EUROPEAN STANDARD . SINGLE 5V SUPPLY

zoran vaddis 888

Abstract: vaddis 888 zoran vaddis 9 zoran vaddis ZR36125 UV618 vaddis 9 vaddis Zoran 888 ZR36120
Contextual Info: ZR36125 Multimedia Controller for PCI Bus Data Sheet Features • Functional superset of ZR36120: includes support for PCI Subsystem ID and Subsystem Vendor ID. ■ Glueless interface to PCI bus. PCI spec. 2.1 compliance . ■ Glueless interface to MPEG decoders (e.g., ZR36100/

Contextual Info: Z4ÉRAN ZR36125 Multimedia Controller for PCI Bus Data Sheet Features • Functional superset of ZR36120: includes support for PCI Subsystem ID and Subsystem Vendor ID. Video output: 15- and 16-bit RGB pixel formats, as well as 24-bit packed and unpacked , and YUV 4:2:2.

Contextual Info: Crystal Oscillators Crystal Clock Oscillators VCXO Type $ V C X O ^ ^ T ^ COL 5. OV Operating Conditions Operating Temperature KlttSJtiEH Supply V o i tage -10 ~ +70 °C +5. 0V ± 5 % Control Voltage 9JflP«E +2. 5V ± 2. 0V Specifications ttH Parameters

tda5030

Abstract: TDA5030A TDA5030AT ks-2n TDA5030AN vhf linear amplifier TDA5030ATD sot163a saw oscillator 300MHz tuner tv if 36MHz
Contextual Info: TDA5030A Signetics VHF Mixer/Oscillator Circuit Product Specification Linear Products PIN CONFIGURATIONS DESCRIPTION FEATURES The TDA5030A performs the VHF mixer, VHF oscillator, SAW filter IF amplifier, and UHF IF amplifier functions in televi­ sion tuners.

CD74AC191

Abstract: CD74AC191E top 258 pn CD74AC191M CD74ACT191 CD74ACT191E CD74ACT191M
Contextual Info: CD74AC191, CD74ACT191 Data sheet acquired from Harris Semiconductor SCHS243 Presettable Synchronous 4-Bit Binary Up/Down Counter t UCT ROD lacemen P E T p OLE d Re OBS mende ecom No R October 1998 Features Description • Buffered Inputs The CD74AC191 and CD74ACT191 are asynchronously

Contextual Info: CD54AC191, CD54ACT191 Data sheet acquired from Harris Semiconductor SCHS243A Presettable Synchronous 4-Bit Binary Up/Down Counter October 1998 - Revised May 2000 Features Description • Buffered Inputs The CD54AC191 and CD54ACT191 are asynchronously presettable binary up/down synchronous counters that utilize

Contextual Info: SGS-THOMSON ST7162 UNIVERSAL PROGRAMMABLE DUAL PLL PRODUCT PREVIEW • TWO INDEPENDENT PLL WITH 16 BITS PROGRAMMABLE DIVIDERS FROM 13 TO 65535 FOR TRANSMIT AND RECEIVE LOOPS ■ ON CHIP REFERENCE OSCILLATOR COM­ MON FOR THE TWO LOOPS UP TO 16MHz WITH EXTERNAL CRYSTAL

top 258 pn

Contextual Info: CD54AC191, CD54ACT191 Data sheet acquired from Harris Semiconductor SCHS243A Presettable Synchronous 4-Bit Binary Up/Down Counter October 1998 - Revised May 2000 Features Description • Buffered Inputs The CD54AC191 and CD54ACT191 are asynchronously presettable binary up/down synchronous counters that utilize

em 18 reader module pin diagram

Abstract: h t o 2000 varactor tuned oscillator VCXO reeves-hoffman
Contextual Info: la n t 'c c e i a s m EL4584C c c HOlÍZOltíül GetllOCk, 4 F SC HIGH PERFORMANCE ANALOG INTEGRATED CIRCUITS Features General Description • 36MHz, general purpose PLL The EL4584C is a PLL Phase Lock Loop sub system, designed for video applications but also suitable for general purpose use up to

IMISC450

Abstract: 2 pin crystal oscillator 20mhZ crystal oscillator 1 MHz 4 pins Crystal 25mhz
Contextual Info: INTL M I C R O C I R C U I T S INC 4ÔE D 4Û 50 41 Û 0 0 0 Q S M 2 3Eâ IM I CLOCK CHIP IHT \ T-5Ô -Z3 IM IS C 4 5 FEATURES DESCRIPTION • ■ The IMISC450 is a clock chip that uses one crystal oscillator to generate 4 independent outputs. One output always has the frequen­

dvb power supply circuit diagram

Abstract: u4744B dvb t receiver circuit diagram dvb t cable receiver circuit diagram U4744
Contextual Info: Temic U4476B S e m i c o n d u c t o r s IF Amplifier / Converter for DVB Cable Description The U4476B is a bipolar circuit for the processing of DVB-Cable IF signals (Digital Video Broadcasting). The amplifier/ converter is suitable for QAM modulated IF

CD74AC191

Abstract: CD54AC191 CD54AC191F3A CD54ACT191 CD54ACT191F3A CD74ACT191
Contextual Info: CD54AC191, CD54ACT191 Data sheet acquired from Harris Semiconductor SCHS243A Presettable Synchronous 4-Bit Binary Up/Down Counter October 1998 - Revised May 2000 Features Description • Buffered Inputs The CD54AC191 and CD54ACT191 are asynchronously presettable binary up/down synchronous counters that utilize