FEATURES CYPRESS FLASH 370 Search Results

Contextual Info: W CYPRESS CY7C373Ì UltraLogic 64-Macrocell Flash CPLD Functional Description Features • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface

319S2

Contextual Info: WFw CYPRESS CY7C374Ì ADVANCED INFORMATION UltraLogic 128-Macrocell Flash CPLD Features • 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR™ Flash technology — JTAG interface

C1573

Abstract: sim 300
Contextual Info: Miuiouay, úo^ioiiiuvi tn, 199& Revision: Tuesday, December 22,1992 •fi»«* n i W «! S7E D 5 5 5 ^ 2 C YP RE S S SEMI CONDUCTOR ODDTOMl ICYP 3bl CY7C375 PRELIMINARY CYPRESS SEMICONDUCTOR 128-Macrocell FLASH PLD Features Functional Description • 128 macroceils in eight logic blocks

Contextual Info: fax id: 6137 CY7C372Ì ^CYPRESS UltraLogic 64-Macrocell Flash CPLD Features • • • • F LA SH 370i™ family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the C Y 7 C 3 7 2 i is de­ signed to bring the ease of use and high performance of the

Contextual Info: UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 m acrocells in four logic blocks T h e CY7C373 is a Flash erasable Com plex Program m able Logic Device C PL D and is p a rt o f th e F lash 370 ” family o f highdensity, high-speed C PLD s. Like all m em ­

schematic flash disk

Abstract: CY3140 ABEL
Contextual Info: PRELIMINARY CY3140 ABEL /Synario™ Design Kit for FLASH370i™ Features System Requirements • Device independent design entry formats: — ABEL-HDL for ABEL-4, ABEL-5, and ABEL-6 — Schematic entry, VHDL, and ABEL-HDL for Synario™ • Full integration supporting all ABEL™ and Synario™

u2330

Contextual Info: fax id: 6126 CY7C371 p ro : V « *1 X X - UltraLogic 32-Macrocell Flash CPLD F lash 370 family, the CY7C371 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. Feat ures • 32 m acrocells in two logic blocks The 32 macrocells in the CY7C371 are divided between two

flash370i isr kit

Abstract: cypress ultra37000 jtag
Contextual Info: CY3600i FLASH370i ISR™ Programming Kit Features programming cable connects to the parallel port of a PC into a standard 10-pin male connector mounted on the user’s board. • Supports FLASH370i and Ultra37000™ devices For Ultra37000V 3.3V support, please see the Ultra37000

Contextual Info: Features « 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — fMAx = 100 MHz — tpo = 12 ns — ts = 7 ns " tco = 7 ns • Electrically Alterable Flash technology • Available in 84-pin PLCC, 84-pin

Contextual Info: fax id: 6140 CY7C375Ì :/ C Y P R E S S UltraLogic 128-Macrocell Flash CPLD Features • • • • Functional Description 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology

Contextual Info: PALCE16V8 V CYPRESS Features • • A ctive p u ll-u p on d ata in p u t p in s • Low pow er version 16V 8L • • — 5 5 m A m ax. com m ercial (1 0 ,1 5 ,2 5 n s) — 65 mA max. industrial (1 0 ,1 5 ,2 5 ns) — 65 m A m ilitary (15 an d 25 n s) •

CY7C373

Abstract: CY7C374 FLASH370 CY7C374-83GC
Contextual Info: 7C373: Thursday, September 24, 1992 Revision: October 14, 1995 CY7C374 UltraLogict 128ĆMacrocell Flash CPLD D D D 128 macrocells in eight logic blocks 64 I/O pins The 128 macrocells in the CY7C374 are diĆ vided between eight logic blocks. Each logic block includes 16 macrocells, a 72 x

Contextual Info: PRELIMINARY C Y 7C 374i UltraLogic 128-Macrocell Flash CPLD Features • • • • 128 macrocells in eight logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface • Bus Hold capabilities on all l/Os and dedicated inputs

allocator

Contextual Info: CY7C373Ì PRELIMINARY UltraLogic 64-Macrocell Flash CPLD Features Device CPLD and is part of the FLASH370i™ family of high-density, high­ speed CPLDs. Like all members of the F lash 37(H family, the CY7C373i is de­ signed to bring the ease of use and high

cypress flash 370

Abstract: logic block diagram of cypress flash 370 device 22v10 CY7C375 FLASH370 o112i cypress flash 370 CPLD cypress flash 370 device technology
Contextual Info: fax id: 6130 For new designs see CY7C375i CY7C375 UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 28 macrocells in eight logic blocks • 28 I/O pins • 6 dedicated inputs including 4 clock pins • Bus Hold capabilities on all I/Os and dedicated inputs

Contextual Info: UltraLogic 128-Macrocell Flash CPLD is designed to bring th e ease o f use and high perform ance o f th e 22V10 to highdensity CPLDs. Features • 128 macrocells in eight logic blocks • 64 I/O pins T he 128 m acrocells in th e CY7C374 are di­ vided betw een eight logic blocks. Each

Contextual Info: PSoC Creator Component Datasheet Timer 2.40 Features • Fixed-function FF and universal digital block (UDB) implementations •    8-, 16-, 24-, or 32-bit timer Optional capture input Enable, trigger, and reset inputs, for synchronizing with other components

7 segment display LT 542

Abstract: LT 542 seven segment display 7 SEGMENT DISPLAY LT 543 PIN CONFIGURATION 7 SEGMENT DISPLAY LT 543 LT 543 7-segment display LT 543 7 segment display 7 SEGMENT DISPLAY LT 543 PIN CONFIGURATION diagram display 7 segment lt 542 PIN DIAGRAM OF 7 segment display LT 543 SEVEN SEGMENT DISPLAY LT 542
Contextual Info: CY8CKIT-006 PSoC 3 LCD Segment Drive Evaluation Kit Guide Doc. # 001-52798 Rev. *C Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone USA : 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com [+] Feedback Copyrights Copyrights

Contextual Info: 6. Dual Input 8-Bit Incremental ADC Dual Input 8-Bit Incremental ADC Data Sheet Dual Input ADC 7 - 13 DualADC8 vX.Y Copyright 2001-2008. Cypress Semiconductor. All Rights Reserved. PSoC Blocks Resources API Memory Bytes Digital Analog CT Analog SC Flash

84 PIN CERAMIC QUAD FLAT PACK

Abstract: 2600 corning cypress flash 370 7C374-100 7C374-66 7C374L-66 CY7C373 CY7C374 FLASH370 CY7C374-83GC
Contextual Info: fax id: 6129 —— — - = : ! W Æ j r I 1 CY7C374 17 Q Q IT C O O UltraLogic 128-Macrocell Flash CPLD Features The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource— the Programmable Interconnect Matrix PIM . The PIM brings flex­

GI05

Contextual Info: CY7C374i p v p v « *1 X X UltraLogic 128-Macrocell Flash CPLD Feat ures • 1 2 8 m a c r o cel l s in e i gh t l ogi c b l o c k s • 6 4 I/O p i n s • 5 d e d i c a t e d i n p u t s i n c l u d i n g 4 c l oc k pi n s • I n - S y s t e m R e p r o g r a m m a b l e I S R ™ Fl ash t e c h n o l o g y

Contextual Info: 6. Dual Input 7- to 13-Bit Incremental ADC Dual Input 7- to 13-Bit Incremental ADC Data Sheet Dual Input ADC 7 - 13 DualADC vX.Y Copyright 2001-2008. Cypress Semiconductor. All Rights Reserved. PSoC Blocks API Memory Bytes Digital Analog CT Analog SC

FillFactory

Abstract: CYII4SC6600-EVAL dummy 68pin IBIS4-6600 CYII4SE6600AB-QFCH CYII4SM6600AB CYII4SC6600AB-QDC CYII4SE6600AB-QDC CYII4SM6600AB-QDC CYII4SM6600AB-QWC
Contextual Info: IBIS4-6600 CYII4SM6600AB 6.6 MP CMOS Image Sensor Features Description • 2210 H x 3002 (V) Active Pixels ■ 3.5 µm X 3.5 µm Square Pixels ■ 1 inch Optical Format ■ Monochrome or Color Digital Output ■ Frame Rate: ❐ 5 fps (2210 x 3002) ❐ 89 fps (640 x 480)

bayview 52 digi

Abstract: Rancho A56 FD37C669 21164PC CR2032 FDC37C669 connector SAMSUNG tab 2 30 PIN 1496R Alpha 21164PC
Contextual Info: AlphaPC 164SX Motherboard Windows NT User’s Manual Order Number: EC–R57DA–TE Revision/Update Information: This is a new document. September 1997 Digital Equipment Corporation 1997. All rights reserved. Printed in U.S.A. AlphaPC, DIGITAL, DIGITAL Semiconductor, and the DIGITAL logo are trademarks of