FCT329 Search Results

Contextual Info: ADVANCE P54/FCT32952A/C P54/FCT32953A/C 3.3V SSOP QSOP NOTEBOOK LOGIC OCTAL REGISTERED TRANSCEIVER INFORMATION FEATURES Edge-rate Control Circuitry for Significantly Improved Noise Characteristics ESD protection exceeds 2000V 64 mA Sink Current (Com’l), 48 mA (Mil)

FCT329

Contextual Info: IDT74FCT3932-100 FCT32932-100 3.3V LOW SKEW PLL-BASED ADVANCE INFORMATION CMOS CLOCK DRIVER Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • 0.5 MICRON CM O S Technology Guaranteed low skew 16 program m able frequency configurations

fdk vco

Abstract: vco fdk
Contextual Info: IDT74FCT3932 3.3V LOW SKEW PLL-BASED ADVANCE INFORMATION CMOS CLOCK DRIVER Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • path delay should be made to match this output path delay. The PLL consists of the phase/frequency detector, charge

Contextual Info: P54/FCT32952C/D P54/FCT32953C/D 3.3 VOLT OCTAL REGISTERED TRANSCEIVER À FEATURES • Function and Drive Compatible with the Fastest TTL Logic ■ Edge-rate Control Circuitry for Significantly Improved Noise Characteristics ■ Inputs and Outputs Interface with TTL Logic

Contextual Info: P54/FCT32952C/D P54/FCT32953C/D 3.3 VOLT OCTAL REGISTERED TRANSCEIVER 7<- FEATURES

Contextual Info: P54/FCT32952A/C advance P54/FCT32953A/C 3.3V SSOP QSOP NOTEBOOK LOGIC OCTAL REGISTERED TRANSCEIVER in fo r m a tio n À-FEATURES • Edge-rate Control Circuitry for Significantly Improved Noise Characteristics

FCT3932

Abstract: IDT74FCT32932-100 IDT74FCT3932-100 LNK14
Contextual Info: IDT74FCT3932-100, FCT32932-100 LOW SKEW PLL-BASED CLOCK DRIVER COMMERCIAL TEMPERATURE RANGES IDT74FCT3932-100 FCT32932-100 3.3V LOW SKEW PLL-BASED ADVANCE INFORMATION CMOS CLOCK DRIVER Integrated Device Technology, Inc. FEATURES: • • • •

ic 1741

Abstract: 2952c
Contextual Info: 4MN 15 m i P54/FCT32952C/D P54/FCT32953C/D OCTAL REGISTERED TRANSCEIVER FEATURES • Function and Drive Compatible with the Fastest TTL Logic ■ Edge-rate Control Circuitry for Significantly Improved Noise Characteristics ■ inputs and Outputs Interface with TTL Logic

fdk vco

Abstract: fdk vco IM vco fdk
Contextual Info: IDT74FCT3932 3.3V LOW SKEW PLL-BASED ADVANCE INFORMATION CMOS CLOCK DRIVER ì it e g i a t s d D ev ± ;e T ech n o lo g y , In c. FEATURES: • • • • • • • • • • • path delay should be made to match this output path delay. The PLL consists of the phase/frequency detector, charge