F H14 Search Results

Contextual Info: LSI LOGIC L64280 Complex FFT Processor FFTP Preliminary D e scrip tio n T h e L64280 F a s t F o u rie r T ra n sfo rm P r o c e s s o r In ad dition to p erfo rm in g F F T s , th e d e v ic e ca n (F F T P ) is a flo a tin g -p o in t c o m p le x F F T p ro c e s ­

GHW Connectors

Abstract: w33b AM512B RC4640 RC4650 RC5000 R3000 RC3041 2W4A
Contextual Info:
          March 2000 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A. 2000 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in

Contextual Info: Openbus I/F Components - VMEbus User Manual 3.0 3.1 DARF Description Introduction This section describes the Data Address Register File DARF . A general architectural description of the DARF is provided, followed by detailed descriptions of the signal pins

EPF10K50S

Abstract: verilog for 8 point fft vhdl code for FFT 32 point EPF10K100B EPF10K100E EPF10K130E EPF10K200E EPF10K30E EPF10K50E
Contextual Info: FLEX 10KE Embedded Programmable Logic Devices January 2001, ver. 2.2 Data Sheet • Features. ■ ■ f Embedded programmable logic devices PLDs , providing system-on-a-programmable-chip integration in a single device – Enhanced embedded array for implementing megafunctions

Contextual Info: in te f 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

C732B

Abstract: 337 BGA 337 BGA footprint EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE
Contextual Info: MAX 7000A Includes MAX 7000AE Programmable Logic Device Family August 2000, ver. 3.1 Data Sheet • Features. ■ ■ ■ ■ ■ ■ ■ f High-performance 3.3-V EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

toshiba 2400 dpi cis sensor

Abstract: CCD LINEAR SENSOR 512 GL842 12 line ccd scanner ccd scanner Genesys Logic scanner 4Mx1 sram canon ccd usb ccd controller ic CCD linear 2400
Contextual Info: Xu062 f Genesys Logic, Inc. GL842 USB 2.0 2-in-1 Scanner Controller Datasheet Revision 1.00 Nov. 14, 2003 GL842 USB 2.0 2-in-1 Scanner Controller Copyright: Copyright 2003 Genesys Logic Incorporated. All rights reserved. No part of the materials may be

Contextual Info: Military COTS 28 Vin Filter M-FIAM9 Model Number M-FIAM9M21* Input Attenuator Module Features • EMI filtering-MIL-STD-461E 1 • Transient protection-MIL-STD-704A/E/F, MIL-STD-1275A/B/D • Environments-MIL-STD-810, MIL-STD-202 • Environmental stress screening

Contextual Info: Military COTS 28 Vin Filter M-FIAM5B Model Number M-FIAM5BM21* Input Attenuator Module Features • • • • • • • • • EMI filtering-MIL-STD-461E 1 Transient protection-MIL-STD-704E/F Environments-MIL-STD-810, MIL-STD-202 Environmental stress screening

Contextual Info: MN34041PL 1.1 Product Summary • Outline This is a MOS-type sensor of 1/3 type offering 2.1 mega pixels. This product consists of embedded photodiode, pixel block by MOS transistor, column AD converter, built-in timing generator TG , high speed serial output I/F and functional

Contextual Info: MN34041PL 1.1 Product Summary • Outline This is a MOS-type sensor of 1/3 type offering 2.1 mega pixels. This product consists of embedded photodiode, pixel block by MOS transistor, column AD converter, built-in timing generator TG , high speed serial output I/F and functional

Contextual Info: Military COTS 28 Vin Filter M-FIAM7 Model Number M-FIAM7M21* Input Attenuator Module Features • EMI filtering-MIL-STD-461E 1 • Transient protection-MIL-STD-1275A/B/D, MIL-STD-704A-F and DO-160E • Environments-MIL-STD-810, MIL-STD-202 • Environmental stress screening

VE-200

Abstract: VE-J00
Contextual Info: FIAM 72 V Input Actual size: 2.28 x 2.2 x 0.5 in 57,9 x 55,9 x 12,7 mm Filter Input Attenuator Module Features Absolute Maximum Rating • RoHS Compliant with F or G pin style • EMI filtering-EN50121-3-2* • Transient protection-EN50155, • • •

Contextual Info: ß fö H O M O K lM lf intei M82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS High Performance 32-Bit DMA Controller — 40 MBytes/sec Maximum Data Transfer Rate at 20 MHz — 8 Independently Programmable Channels DRAM Refresh Controller

ib17

Contextual Info: M D M M ! 0 M [F © [s ]ß M ? 0 © M SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining

spw 068

Contextual Info: Accelerator Series FPGAs - ACT 3 Family F e a tu re s • Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent PLD Gates • Replaces up to one hundred 20-pin PAL Packages • Highly Predictable Performance with 100% Automatic

Contextual Info: intei A D W M C B O M IF Û fô G M T tM M82370 INTEGRATED SYSTEM PERIPHERAL Programmable Walt State Generator — 0 to 15 Wait States Pipelined — 1 to 16 Wait States Non-Pipelined High Performance 32-Blt DMA Controller for 16-Bit Bus — 16 MBytes/Sec Maximum Data

AGL400

Abstract: TOP MARK E6 T7IO192NPB3
Contextual Info: IGLOO Packaging 3 – Package Pin Assignments 81-Pin µCSP A1 Ball Pad Corner 9 8 7 6 5 4 3 2 1 A B C D E F G H J Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at .

12 line ccd scanner

Abstract: toshiba 2400 dpi cis sensor nec CCD LINEAR IMAGE SENSOR flatbed scanner controller CCD LINEAR SENSOR 512 linear ccd ST L6219 application note block diagram of paper scanner CCD linear 10 ccd sony
Contextual Info: Ru.4 Xu062 f Genesys Logic, Inc. GL848 High Speed USB 2.0 2-in-1 Scanner Controller With Fast ADF & Bus Power Datasheet Revision 1.00 December 17, 2007 GL848 High Speed USB2.0 2-in-1 Scanner Controller With Fast ADF Copyright: Copyright 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be

CAPT3216

Abstract: PAD35 PTC1111 I82559ER l28c PTC111 HEAD2X10 ptc1111-00 8 pin LM393 ic for 12v swdip
Contextual Info: A B C D E F G H 1 1 80312/Coyanosa DECOUPLING SPCI DECOUPLING IC DECOUPLING +3V +3V SDRAM DECOUPLING +3V +3V +3V +3V +5V +3V +5V 2 C139 1 2 C61 1 2 C161 1 2 2 3 4 5 CAPT7343 47uF C23 2 1 CAP0805 0.1uF C154 2 1 CAP0805 0.1uF C117 2 1 CAP0805 0.1uF C22 2 1 CAP0805

729-Pin

Abstract: Axcelerator FPGAs AX125 IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs
Contextual Info: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at

Contextual Info: SMJ34020A GRAPHICS SYSTEM PROCESSOR SGUS011D - APRIL 1991 - REVISED SEPTEMBER 2004 D D D D D D D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G H J K L M N P R 132-PIN QUAD FLATPACK TOP VIEW 100 D 145-PIN GRID ARRAY PACKAGE (TOP VIEW) 1 99 33 67 66

IO51NDB1V0

Abstract: IO83NPB4V0 IO10PDB0V1
Contextual Info: Actel Fusion Mixed-Signal FPGA for the MicroBlade AdvancedMC Solution 4 – Package Pin Assignments 256-Pin FBGA A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Note For Package Manufacturing and Environmental information, visit the Resource Center at

Contextual Info: REVISIONS LTR DESCRIPTION A B C D E F G DATE YR-MO-DA APPROVED 93-06-15 94-04-18 95-03-25 95-06-08 99-11-15 05-04-13 13-04-24 M. L. Poelking M. L. Poelking M. L. Poelking Thomas M. Hess M. L. Poelking Thomas M. Hess Thomas M. Hess Changes in accordance with NOR 5962-R144-93