F 6553 Search Results

a7y transistor

Abstract: RASH UD61466 A7X k
Contextual Info: Maintenance only UD61466 64K x 4 DRAM Features F Dynamic random access memory F F F F F F F F F F F 65536 x 4 bits manufactured using a CMOS technology RAS access times 70 ns/80 ns TTL-compatible Three-state outputs bidirectional 256 refresh cycles 4 ms refresh cycle time

m5M28F102

Contextual Info: MITSUBISHI LSIs M 5 2 8 M 1 0 2 F F P , J , V P , R V - 1 0 1 2 , - 1 5 , - 1048576-BIT 65536-WORD BY 16-BIT CMOS FLASH MEMORY DESCRIPTION The M its u b is h i PIN CONFIGURATION (TOP VIEW) M 5 M 2 8 F 1 0 2 F P , J , V P , RV are h ig h - s p e e d 1 0 4 8 5 7 6 - b it C M OS Flash M e m orie s. T h e y are s u ita b le fo r

sc2625

Abstract: RC32364 RC3041 RC4640 RC4650 RC5000
Contextual Info:

         Version 1.0 December 1999 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A. 1999 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

RC3041

Abstract: RC32364 RC4640 RC4650 RC5000
Contextual Info:

         Version 1.0 December 1999 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A. 1999 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

PLL2001

Contextual Info: - 334 - S S I C • N J M 2 2 6 0 fiH * xt m tt « « 1 6 : iti f 'J Ì # , f f i S É l i , Ì S Ì 7 > y m g «A ) 5È * ft E n * /J' a * (400MHz ~ 1GHz) „ Vcc(V) 8 .0 Ta=25°C » f¥ *S 3E E *S H : IF i f l f i i k i ' Icc(mA) 22. 0 Vcc=8V rS S S »

H8S/2319

Abstract: HD6412312VF DATASHEET H8S/2320 H8S/2317 H8S/2338 F-ZTAT H8S/2312 PE2D HD6412312VTE P13DR
Contextual Info: Hitachi 16-Bit Single-Chip Microcomputer H8S/2319, H8S/2318 Series, H8S/2319 F-ZTAT , H8S/2318 F-ZTAT™, H8S/2315 F-ZTAT™ H8S/2319 H8S/2318 H8S/2317 H8S/2316 H8S/2315 H8S/2313 H8S/2312 H8S/2311 H8S/2310 HD64F2319 HD6432318, HD64F2318 HD6432317 HD6432316

cxa 21040

Abstract: TLC2654 TLC2654A TLC2654AC-8D TLC2654ACP TLC2654C-8D TLC2654Y
Contextual Info: TLC2654, TLC2654A, TLC2654Y Advanced LinCMOSTM LOW-NOISE CHOPPER-STABILIZED OPERATIONAL AMPLIFERS SLQS020D - NOVEMBER 1988 - REVISED AUGUST 1994 Input Noise Voltage 0.5 jlV Peak-to-Peak Typ, f = 0 to 1 Hz 1.5 fiV (Peak-to-Peak) Typ, f = 0 to 10 Hz 47 nV/VRz Typ, f = 10 Hz

RC32300

Abstract: c3233 ATMEL Packaging and labeling guideline MIPS r3000 RC32300 datasheet IDT RC32334 Users Manual jm 60 ac
Contextual Info:
    
   
            
        !   "     November 2000 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674

tlc2654

Contextual Info: TLC2654, TLC2654A, TLC2654Y Advanced LinCMOS LOW-NOISE CHOPPER-STABILIZED OPERATIONAL AMPLIFIERS SLOS020E - NOVEMBER 1988 - REVISED FEBRUARY 1999 Input Noise Voltage 0.5 jaV Peak-to-Peak Typ, f = 0 to 1 Hz 1.5 jaV (Peak-to-Peak) Typ, f = 0 to 10 Hz 47 nV/VFjz Typ, f = 10 Hz

a733c

Contextual Info: UA733C, u A 7 3 3 M D I F F E R E N T I A L VIDEO A M P L I F I E R S S LFS 027A -D 922, NOVEMBER 1 9 7 0 - REVISED MARCH 1993 * 200-MHz Bandwidth u A733C . . . D OR N PA CKAGE

Contextual Info: Qrjf.fle nuT.bqr; EHÌ035A _ I S .W 8S A ?fMQÆL$l Ë M T O 8 S , 7 0 0 6 H r f / Dual IJLL Frequency Synthesizer Circuit ÛTflrvifiv T h e I^.V17 CilHG, 70[ifhEl Lr ;î P L L S ju lh c B iïG r c ir c u ii Fût llsç ln cu n lle u s te le p h a n e a , I t incürptft i t d f i t p f i m t p q | i U i i n i h l t d i v t t k r j , u h a ic c o m p a ra to rs u n d daal^j ^ f n c h u rg e p u m p a f a r ìéié: L rïinam it

PLL2001

Abstract: pll*2001 pll200 801C rigel
Contextual Info: ^ f \ J P C nippon precision circuits ito. • General i F*L_L_2 0 0 1 006805 . V High Speed PLL Synthesizer " f ^ p C T h e N P C P L L 2 0 0 1 is a g e n e r a l p u r p o s e P L L f r e q u e n c y s y n t h e s i z e r es p e c i a l l y d e s i g n e d for a high f r e q u e n c y a p p l i c a t i o n up to 200MHz.

Contextual Info: M IT S U B IS H I M IC RO CO M PUTERS M 3 7 4 5 0 S 1 S P /F P .M 3 7 4 5 0 S 2 S P /F P M 3 7 4 5 0 S 4 S P /F P 8 -B IT CM O S M IC R O C O M P U T E R DESCRIPTION PIN CONFIGURATION TOP VIEW T h e M 3 7 4 5 0 S 1 S P /F P is a sin g le -ch ip m icro com puter d e ­

Contextual Info: FUJITSU MICROELECTRONICS CONTROLLER MANUAL CM44-10106-6E 2 F MC-16LX 16-BIT MICROCONTROLLER MB90595 Series HARDWARE MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90595 Series HARDWARE MANUAL The information for microcontroller supports is shown in the following homepage.

47UF

Abstract: bq2000 bq2000T MMSD914LT PKSMD-1005-470K-1A
Contextual Info: bq2000T Programmable Multi-Chemistry Fast-Charge Management IC Features General Description ➤ Safe m anag e m e nt o f f ast charge for NiCd, NiMH, or LiIon battery packs ➤ High-frequency switching controller for efficient and simple charger design ➤

M50957-XXXSPs

Abstract: 50958-XXXSP
Contextual Info: M IT S U B IS H I M ICRO CO M PUTERS M 5 0 9 5 7 -X X X S P /F P ,M 5 0 9 5 8 -X X X S P /F P preliminary :"»««-*^ M 5 0 9 5 9 -X X X S P /F P mm N otice These are noi a final specification. Some param etric lim its art? subject to change. DESCRIPTION

CD54ACT04F

Contextual Info: CD54ACT04, CD74ACT04 HEX INVERTERS SCHS310B – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54ACT04 . . . F PACKAGE CD74ACT04 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption

ACT00M

Abstract: CD54ACT00 CD54ACT00F3A CD74ACT00 CD74ACT00E CD74ACT00M CD74ACT00M96
Contextual Info: CD54ACT00, CD74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS308B – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54ACT00 . . . F PACKAGE CD74ACT00 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With

Contextual Info: M ii5 u is i» n i m ititu tu m r u i M 3 7 4 5 1 M 4 - X X X S P / F P /G P M 3 7 4 5 1 M 8 - X X X S P / F P /G P M 3 7 4 5 1 M C - X X X S P /F P /G P S IN G L E -C H IP 8 -B IT CMO S M IC R O C O M P U T E R DESCRIPTION The M 37451M 4-X X X S P /F P /G P

Contextual Info: CD54ACT05, CD74ACT05 HEX INVERTERS WITH OPEN-DRAIN OUTPUTS SCHS311B – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54ACT05 . . . F PACKAGE CD74ACT05 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With

Contextual Info: CD54ACT20, CD74ACT20 DUAL 4-INPUT POSITIVE-NAND GATES SCHS320 – NOVEMBER 2002 D D D D D D CD54ACT20 . . . F PACKAGE CD74ACT20 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption

CD74ACT20

Abstract: CD54ACT20 CD54ACT20F3A CD74ACT20E CD74ACT20M CD74ACT20M96 ACT20M
Contextual Info: CD54ACT20, CD74ACT20 DUAL 4-INPUT POSITIVE-NAND GATES SCHS320 – NOVEMBER 2002 D D D D D D CD54ACT20 . . . F PACKAGE CD74ACT20 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption

ACT00M

Abstract: CD54ACT00 CD54ACT00F3A CD74ACT00 CD74ACT00E CD74ACT00M CD74ACT00M96
Contextual Info: CD54ACT00, CD74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCHS308B – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54ACT00 . . . F PACKAGE CD74ACT00 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With

Contextual Info: CD54ACT20, CD74ACT20 DUAL 4-INPUT POSITIVE-NAND GATES SCHS320 – NOVEMBER 2002 D D D D D D CD54ACT20 . . . F PACKAGE CD74ACT20 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption