ERROR CORRECTING CODE Search Results
ERROR CORRECTING CODE Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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74AS632FN |
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74AS632 - 32-Bit Parallel Error Detection/Correction |
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TC4511BP |
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CMOS Logic IC, BCD-to-7-Segment Decoder, DIP16 | Datasheet | ||
29C60APC |
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AM29C60A - Casacadable 16-Bit Error Detection |
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29C60AJC |
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AM29C60A - Casacadable 16-Bit Error Detection |
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54185AJ/B |
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54185A - Binary to BCD Converters |
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ERROR CORRECTING CODE Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: CY7C1062G CY7C1062GE PRELIMINARY 16-Mbit 512 K words x 32 bits Static RAM with Error-Correcting Code (ECC) 16-Mbit (512 K words × 32 bits) Static RAM with Error-Correcting Code (ECC) Features • High speed ❐ tAA = 10 ns ■ Embedded error-correcting code (ECC) for single-bit error |
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CY7C1062G CY7C1062GE 16-Mbit 119-ball | |
Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error co r rection, bit filling and synchronization schem e specified in ITU-TSS formerly CCITT recom m endation H.261. The forw ard error correcting code is a 2-error correcting BCH |
OCR Scan |
L64715 511-bit S3D4fi04 44-Pin 53Q4fl04 | |
BCH codeContextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error cor rection, bit filling and synchronization schem e specified in IT U -T SS formerly CCITT recom m endation H.261. The forward error correcting code is a 2-error correcting BCH |
OCR Scan |
L64715 44-Pin BCH code | |
Contextual Info: CY7C1069G CY7C1069GE PRELIMINARY 16-Mbit 2 M words x 8 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (2 M words × 8 bit) Static RAM with Error-Correcting Code (ECC) Features an error indication pin (ERR) that signals the host processor in the case of an ECC error-detection and correction event. |
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CY7C1069G CY7C1069GE 16-Mbit | |
AT91SAM
Abstract: atmel BCH codes 257975,BOSE atmel 418
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32-bit 11038AS 26-Jan-10 AT91SAM atmel BCH codes 257975,BOSE atmel 418 | |
Contextual Info: Work? Error-correcting codes sums to 0. Thus, calculating the checkbits as shown in Fig Many types of error-correcting techniques exist, but in data ure 1, the data word D15-D„) 0011 1101 1001 1001 yields communications, Hamming encoding probably finds the |
OCR Scan |
16-bit | |
k 4110
Abstract: LC8955 LC8956 zcmd 3151-QIP100E
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ENS3U110 LC8956 LC8956 LC8951 LC8955 100-pin k 4110 zcmd 3151-QIP100E | |
Contextual Info: PRELIMINARY CY7C1061G/CY7C1061GE 16-Mbit 1 M words x 16 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features To access devices with a single chip enable input, assert the chip |
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CY7C1061G/CY7C1061GE 16-Mbit ns/15 90-mA 20-mA | |
Contextual Info: PRELIMINARY CY7C1061G/CY7C1061GE 16-Mbit 1 M words x 16 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features To access devices with a single chip enable input, assert the chip |
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CY7C1061G/CY7C1061GE 16-Mbit ns/15 90-mA 20-mA | |
Contextual Info: CY62168G PRELIMINARY CY62168GE MoBL 16-Mbit 2 M words x 8 bits Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit / 2 M words × 8 bit) Static RAM with Error-Correcting Code (ECC) Features • Ultra-low standby power ❐ Typical standby current: 3.2 A |
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CY62168G CY62168GE 16-Mbit 48-ball | |
CY7S1061GContextual Info: PRELIMINARY CY7S1061G, CY7S1061GE 16-Mbit 1 M words x 16 bit Static RAM with Deep-Sleep Feature and Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Deep-Sleep Feature and Error Correcting Code (ECC) Features To access devices with a single-chip enable input, assert the chip |
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CY7S1061G, CY7S1061GE 16-Mbit 90-mA 20-mA CY7S1061G | |
Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Preliminary Description The L64715 implements the forward error cor rection, bit filling and synchronization scheme specified in International Consultative Committee for Telephones and Telegraphs |
OCR Scan |
L64715 L64715 44-Pin | |
Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error co r rection, bit filling and synchronization scheme specified in CCITT Consultative Committee on International Telephones and Telegraphs recom m endation H.261. The forw ard error |
OCR Scan |
L64715 L64715 44-Pin | |
AK4110Contextual Info: SANYO SEMICONDUCTOR CORP S3E D T T ì T Q T b D D 1 D 2 Ö Q TÔ3 « T S A J number: ENÌSS4110 T - 7 5 - 11-07 CMOS LSI No. ÌK4110 S A \Y O i LC8956 Error-Correcting and ADPCM Decoder IC for CD-I/CD-ROM XA Systems Preliminary OVERVIEW PINOUT The LC8956 is an error-correcting and ADPCM decod |
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SS4110 K4110 LC8956 LC8956 LC8951 LC8955 AK4110 | |
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Contextual Info: LSI LOGIC L64710 8-Error Correcting Reed-Solomon Codec Description The L64710 contains an RS Reed-Solomon encoder and a RS decoder. This pipelined, high-speed, error-correction device im ple ments an RS code as specified in CMTT (Committee fo r Mixed Telephone and |
OCR Scan |
L64710 L64710 CCIR723. 68-Pin MIL-STD-883C | |
fsk modulator demodulator
Abstract: 89C026LT block diagram of laptop 89C024LT PLCC 68 intel
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89C024LT RS-232/V 89C026LT fsk modulator demodulator 89C026LT block diagram of laptop PLCC 68 intel | |
Contextual Info: CY7C10612G CY7C10612GE PRELIMINARY 16-Mbit 1 M x 16 Static RAM 16-Mbit (1 M × 16) Static RAM Features • High speed ❐ tAA = 10 ns ■ Embedded error-correcting code (ECC) for single bit error correction ■ Low active power ❐ ICC = 90mA typical ■ |
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CY7C10612G CY7C10612GE 16-Mbit 54-pin | |
Contextual Info: APRIL 1995 MA31755 DS3572-2.3 MA31755 16-BIT FEEDTHROUGH ERROR DETECTION & CORRECTION UNIT EDAC The MA31755 is a 16 bit Error Detection and Correction Unit intended for use in high integrity systems for monitoring and correcting data values retrieved from memory. The EDAC |
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MA31755 DS3572-2 16-BIT MA31755 | |
SY006
Abstract: bit-slice SY107 A132A SY105 808-1 SYL alb phoenix me SY03 SY16
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MC109O5 16-BIT MCI0905 SY006 bit-slice SY107 A132A SY105 808-1 SYL alb phoenix me SY03 SY16 | |
Contextual Info: DP8400-2 5 National Semiconductor DP8400-2—E2C2 Expandable Error Checker/Corrector General Description The DP8400-2 Expandable Error Checker and Corrector E2C2 aids system reliability and integrity by detecting er rors in memory data and correcting single or double-bit er |
OCR Scan |
DP8400-2 DP8400-2â DP8400-2 48-pin DP8400-2S DP8400-2/8409A 16-Blt | |
MA31750 processor architecture
Abstract: MA31750 DS3572-4 edac MA31755 DS3572-3 md08
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MA31755 16-Bit DS3572-3 MA31755 MA31750 processor architecture MA31750 DS3572-4 edac md08 | |
MA31750
Abstract: MA31750 processor architecture MA31755 XG451 CS1N CB05
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MA31755 16-Bit DS3572-4 MA31755 MA31750 MA31750 processor architecture XG451 CS1N CB05 | |
Contextual Info: P^pi GEC PLESSEY PRELIMINARY INFORMATION DS3569-2.4 MA31752 16-BIT FEEDTHROUGH ERROR DETECTION & CORRECTION UNIT EDAC The MA31752 is a 16 bit Error Detection and Correction Unit intended for use in a high integrity system for monitoring and correcting data values retrieved from memory. The EDAC |
OCR Scan |
DS3569-2 MA31752 16-BIT MA31752 MA31750 68-pin MA31750 | |
atmel edac
Abstract: 1X1-21-1 nxor TPD16 29C532E
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29C532E 32-Bit 29C532E tpd16 atmel edac 1X1-21-1 nxor TPD16 |