ERROR CORRECTING CODE Search Results

Contextual Info: CY7C1062G CY7C1062GE PRELIMINARY 16-Mbit 512 K words x 32 bits Static RAM with Error-Correcting Code (ECC) 16-Mbit (512 K words × 32 bits) Static RAM with Error-Correcting Code (ECC) Features • High speed ❐ tAA = 10 ns ■ Embedded error-correcting code (ECC) for single-bit error

Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error co r­ rection, bit filling and synchronization schem e specified in ITU-TSS formerly CCITT recom m endation H.261. The forw ard error correcting code is a 2-error correcting BCH

BCH code

Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error cor­ rection, bit filling and synchronization schem e specified in IT U -T SS formerly CCITT recom m endation H.261. The forward error correcting code is a 2-error correcting BCH

Contextual Info: CY7C1069G CY7C1069GE PRELIMINARY 16-Mbit 2 M words x 8 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (2 M words × 8 bit) Static RAM with Error-Correcting Code (ECC) Features an error indication pin (ERR) that signals the host processor in the case of an ECC error-detection and correction event.

AT91SAM

Abstract: atmel BCH codes 257975,BOSE atmel 418
Contextual Info: Features • Multibit Error Correcting Code • Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem BCH codes Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 bit of errors per sector Programmable Sector Size: 512 bytes or 1024 bytes.

Contextual Info: Work? Error-correcting codes sums to 0. Thus, calculating the checkbits as shown in Fig­ Many types of error-correcting techniques exist, but in data ure 1, the data word D15-D„) 0011 1101 1001 1001 yields communications, Hamming encoding probably finds the

k 4110

Abstract: LC8955 LC8956 zcmd 3151-QIP100E
Contextual Info: Ordering number: E N & 4 1 1 0 _ CMOS LSI No. &4110 _ LC8956 Error-Correcting and ADPCM Decoder 1C for CD-I/CD-ROM XA Systems Preliminary PINOUT OVERVIEW The LC8956 is an error-correcting and ADPCM decod­

Contextual Info: PRELIMINARY CY7C1061G/CY7C1061GE 16-Mbit 1 M words x 16 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features To access devices with a single chip enable input, assert the chip

Contextual Info: PRELIMINARY CY7C1061G/CY7C1061GE 16-Mbit 1 M words x 16 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features To access devices with a single chip enable input, assert the chip

Contextual Info: CY62168G PRELIMINARY CY62168GE MoBL 16-Mbit 2 M words x 8 bits Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit / 2 M words × 8 bit) Static RAM with Error-Correcting Code (ECC) Features • Ultra-low standby power ❐ Typical standby current: 3.2 A

CY7S1061G

Contextual Info: PRELIMINARY CY7S1061G, CY7S1061GE 16-Mbit 1 M words x 16 bit Static RAM with Deep-Sleep Feature and Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Deep-Sleep Feature and Error Correcting Code (ECC) Features To access devices with a single-chip enable input, assert the chip

Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Preliminary Description The L64715 implements the forward error cor­ rection, bit filling and synchronization scheme specified in International Consultative Committee for Telephones and Telegraphs

Contextual Info: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error co r­ rection, bit filling and synchronization scheme specified in CCITT Consultative Committee on International Telephones and Telegraphs recom m endation H.261. The forw ard error

AK4110

Contextual Info: SANYO SEMICONDUCTOR CORP S3E D T T ì T Q T b D D 1 D 2 Ö Q TÔ3 « T S A J number: ENÌSS4110 T - 7 5 - 11-07 CMOS LSI No. ÌK4110 S A \Y O i LC8956 Error-Correcting and ADPCM Decoder IC for CD-I/CD-ROM XA Systems Preliminary OVERVIEW PINOUT The LC8956 is an error-correcting and ADPCM decod­

Contextual Info: LSI LOGIC L64710 8-Error Correcting Reed-Solomon Codec Description The L64710 contains an RS Reed-Solomon encoder and a RS decoder. This pipelined, high-speed, error-correction device im ple­ ments an RS code as specified in CMTT (Committee fo r Mixed Telephone and

fsk modulator demodulator

Abstract: 89C026LT block diagram of laptop 89C024LT PLCC 68 intel
Contextual Info: 89C024LT ERROR CORRECTING LAPTOP MODEM CHIP SET CHMOS for Low Operating Power Low Standby Power Requirements Minimum Chip Count for Small size MNP* Operation through Class 4 for Error Correction MNP Class 5 Data Compression for Increased Throughput AT Command Set

Contextual Info: CY7C10612G CY7C10612GE PRELIMINARY 16-Mbit 1 M x 16 Static RAM 16-Mbit (1 M × 16) Static RAM Features • High speed ❐ tAA = 10 ns ■ Embedded error-correcting code (ECC) for single bit error correction ■ Low active power ❐ ICC = 90mA typical ■

Contextual Info: APRIL 1995 MA31755 DS3572-2.3 MA31755 16-BIT FEEDTHROUGH ERROR DETECTION & CORRECTION UNIT EDAC The MA31755 is a 16 bit Error Detection and Correction Unit intended for use in high integrity systems for monitoring and correcting data values retrieved from memory. The EDAC

SY006

Abstract: bit-slice SY107 A132A SY105 808-1 SYL alb phoenix me SY03 SY16
Contextual Info: MC109O5 16-BIT EXPANDABLE ERROR DETECTION AND CORRECTION UNIT The MCI0905 is a high speed 16-bit error detection and correction unit that is easily expandable to handle up to 96 data bits. The unit is designed to improve the reliability of memory systems by detecting and correcting any single bit error while detecting

Contextual Info: DP8400-2 5 National Semiconductor DP8400-2—E2C2 Expandable Error Checker/Corrector General Description The DP8400-2 Expandable Error Checker and Corrector E2C2 aids system reliability and integrity by detecting er­ rors in memory data and correcting single or double-bit er­

MA31750 processor architecture

Abstract: MA31750 DS3572-4 edac MA31755 DS3572-3 md08
Contextual Info: MA31755 MA31755 16-Bit Feedthrough Error Detection & Correction Unit EDAC Replaces June 1999 version, DS3572-3.0 The MA31755 is a 16 bit Error Detection and Correction Unit intended for use in high integrity systems for monitoring and correcting data values retrieved from memory. The EDAC

MA31750

Abstract: MA31750 processor architecture MA31755 XG451 CS1N CB05
Contextual Info: MA31755 MA31755 16-Bit Feedthrough Error Detection & Correction Unit EDAC Replaces January 2000 version, DS3572-4.0 The MA31755 is a 16 bit Error Detection and Correction Unit intended for use in high integrity systems for monitoring and correcting data values retrieved from memory. The EDAC

Contextual Info: P^pi GEC PLESSEY PRELIMINARY INFORMATION DS3569-2.4 MA31752 16-BIT FEEDTHROUGH ERROR DETECTION & CORRECTION UNIT EDAC The MA31752 is a 16 bit Error Detection and Correction Unit intended for use in a high integrity system for monitoring and correcting data values retrieved from memory. The EDAC

atmel edac

Abstract: 1X1-21-1 nxor TPD16 29C532E
Contextual Info: 29C532E 32-Bit Bus-Watch EDAC Error Detection And Correction unit 1. Description The 29C532E EDAC is a very low power bus-watch 32-bit Error Detection And Correction unit EDAC . EDAC is used in a high integrity system for monitoring and correcting data values coming from the memory