EQUATION Search Results

Contextual Info: DM5438,DM7438 DM5438 DM7438 Quad 2-Input NAND Buffers with Open-Collector Outputs Literature Number: SNOS255A DM5438 DM7438 Quad 2-Input NAND Buffers with Open-Collector Outputs General Description Pull-Up Resistor Equations RMAX e VCC Min b VOH N1 (IOH) a N2 (IIH)

Programmable Divider

Abstract: 20MHZ 400M AL2007LA STD90 embedded PLL divider
Contextual Info: 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA GENERAL DESCRIPTION The AL2007LA is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macrofunctions provide frequency multiplication capabilities. The output clock frequency Fout is related to the reference input clock frequency Fin by the following equation:

lf XTAL 20MHz

Abstract: XTAL 20MHz 20MHZ PLL2013X STD110
Contextual Info: 0.25µ µm 20MHz~170MHz FSPLL PLL2013X GENERAL DESCRIPTION The PLL2013X is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macro-functions provide frequency multiplication capabilities. The output clock frequency Fout is related to the input clock frequency Fin(XTALIN) by the following equation:

MIL-STD-806B

Abstract: MIL-STD-806 toggle nand hct mos Transmission gate IC
Contextual Info: Logic Sym bols and Truth Tables C2M O S Logic TC74HC/HCT Series 6. How to Read MIL Type Logic Symbols and Truth Tables Table 6-1. MIL Logic Symbols Circuit Logical Equation or Truth Logic Sym bol Function Table 6-1 How to Read MIL Type Logic Symbols Table 6-1 shows the MIL type logic symbols used in high-speed

DM7407M

Abstract: DM7407N DM5407J DM5407 DM5407W DM7407 J14A M14A N14A W14B
Contextual Info: DM5407 DM7407 Hex Buffers with High Voltage Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains six independent gates each of which performs a buffer function The open-collector outputs require external pull-up resistors for proper logical operation

DM5401

Abstract: C1995 DM5401J DM5401W DM7401 DM7401N J14A N14A W14B
Contextual Info: DM5401 DM7401 Quad 2-Input NAND Gates with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains four independent gates each of which performs the logic NAND function The open-collector outputs require external pull-up resistors for proper logical operation

Contextual Info: June 1989 DM5405/DM7405 Hex Inverters with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains six independent gates each of which performs the logic INVERT function. The open-collector out­ puts require external pull-up resistors for proper logical op­

DM7416N

Abstract: DM5416J DM7416 C1995 DM5416 DM5416W J14A N14A W14B dm7416 national
Contextual Info: DM5416 DM7416 Hex Inverting Buffers with High Voltage Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains six independent gates each of which performs the logic INVERT function The open-collector outputs require external pull-up resistors for proper logical operation

Contextual Info: TITLE Design Equations DOCUMENT No. REV PAGE DESIGN EQUATIONS - 1

DM7406 FAIRCHILD

Abstract: DM7406N DM7406 DM7406M M14A MS-001 N14A
Contextual Info: Revised July 2001 DM7406 Hex Inverting Buffers with High Voltage Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains six independent buffers each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical

fairchild 7438

Abstract: 7438SJ DM7438 DM7438M DM7438N M14A M14D MS-001 N14A
Contextual Info: Revised July 2001 DM7438 • 7438 Quad 2-Input NAND Buffers with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical

wf_47004.0

Contextual Info: Category: Waveforms & Filters CIRCUIT IDEAS FOR DESIGNERS Schematic no. wf_47004.0 Low-Pass Filter RFI Filter Description This circuit utilizes an operational amplifier to produce a low-pass filter. The input of the low-pass filter has an input resistance of 10K ohm and an input cutoff frequency depending on the product of R1C1 (see equation

AN9510

Abstract: op amp cookbook 748 OP AMP Mancini analog cookbook Op-amp AN9757
Contextual Info: Harris Semiconductor No. AN9757 Harris Linear July 1997 A Cookbook Approach to Single Supply DC-Coupled Op Amp Design Authors: Ron Mancini and Chris Davis Introduction The equation derivation will be done in two parts through the use of superposition. The final output voltage, VO, equals the

662k

Abstract: .662K AN9607 HC5509 HC5509A1R3060 HC5517 525k
Contextual Info: Harris Semiconductor No. AN9607.1 Harris Telecom October 1996 Impedance Matching Design Equations for the HC5509 Series of SLICs Authors: Don LaFontaine and Ed Berrios Introduction R The HC5509 Series of SLICs use feedback to synthesize the impedance at the 2-wire tip and ring terminals. The network

MTTL and MECL Avionics Digital

Abstract: an532 motorola AN532 MC4044 AN532 digital frequency synthesizer MC4024 mc4324 MC4024 pll MC4316 MTTL and MECL Avionics Digital AN532
Contextual Info: AN535 Application Note PhaseĆLocked Loop Design Fundamentals Prepared by Garth Nash Applications Engineering The fundamental design concepts for phase-locked loops implemented with integrated circuits are outlined. The necessary equations required to evaluate the

integer division 4 bits by 2 bits

Abstract: XC4000E
Contextual Info: Pipelined Divider May 28, 1999 Product Specification Dividend=Quotient*Divisor + IntRmd R Equation 1 Dividend = quotient * divisor plus integer remainder. Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com

Contextual Info: ISS. DATE E.C.N. DESCRIPTION 1 02-May-12 FIRST ISSUE 2 11-Feb-04 2/4/1133 EDGE DRAFT INCREASED TO 3° 3 15-Jan-07 SCALLOP SIZE INCREASED TO R3.75 4 19-May-11 05/11/1301 1/07/1199 CUSTOMER DRAWING TIR CURVE DEFINITION REPLACED WITH EQUATION REFINE 25 DIM. TO REF

AN-912

Contextual Info: OVERVIEW The scope of this application note is to introduce common data transmission parameters and to provide their definitions. This application note is subdivided into five sections, which are: ample the receiver’s input terminals. This voltage is referenced to circuit common ground . This parameter is illustrated in Figure 1 along with its mathematical equation.

radix-2 dit fft flow chart

Abstract: 16 point DIF FFT using radix 4 fft 16 point DIF FFT using radix 2 fft 8 point fft radix-2 DIT FFT C code radix-2 Butterfly two butterflies ADSP-2100
Contextual Info: 6 One-Dimensional FFTs 6.2.3 Radix-2 Decimation-In-Frequency FFT Algorithm In the DIT FFT, each decimation consists of two steps. First, a DFT equation is expressed as the sum of two DFTs, one of even samples and one of odd samples. This equation is then divided into two equations, one

Contextual Info: . F98S UDR2 .42 m EQUATION OR T UC POWER @ 50MHZ F98S UDR2 (.42 m) H89G CDR2 (.36 m) EQUATION POWER @ 25MHZ H89G CDR2 (.36 m) POWER @ 50MHZ H89G CDR2 (.36 m) POWER @ 66MHZ H89G CDR2 (.36 m) @20 mW + Fs/50 * (.78)/2DFNH W 800 mW @20 mW + Fs/50 * (.555)/2DFNH W

AD5933 rev. c

Abstract: AD5933 AD5933BRSZ-U1 INFRARED SENSOR
Contextual Info: Preliminary Technical Data 1 MSPS 12-Bit Impedance Converter, Network Analyzer AD5933 point. The magnitude of the impedance and relative phase of the impedance at each frequency point along the sweep is easily calculated using the following equations: FEATURES

Contextual Info: Preliminary Technical Data 250 kSPS 12-Bit Impedance Converter, Network Analyzer AD5934 impedance at each frequency point along the sweep is easily calculated using the following equations: FEATURES 100 kHz max excitation output Impedance range 0.1 kΩ to 10 MΩ, 12-bit resolution

025010

Contextual Info: S E M IC O N D U C T O R T M DM74LS26 Quad 2-Input NAND Gates with High Voltage Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains fo u r independent gates each of which perform s th e logic NAND function. The o pen-collector out­

Contextual Info: ANALO G D EVIC ES high Accuracy 8-Pin Instrumentation Anplifier MP02 FEATURES Low Offset Voltage: 100 jiV max Low Drift: 2 |xV/°C max W ide Gain Range 1 to 10,000 High Com m on-M ode Rejection: 115 dB min High Bandwidth (G = 1000 : 200 kHz typ Gain Equation Accuracy: 0.5% max