EPM5032 MAX Search Results

EPM5032

Abstract: 1PD2 EPM5032 max epm5032-15 EPM5032A Q421 MSI MS-5
Contextual Info: EPM5032 EPLD Features B • ■ ■ ■ MAX 5000 ■ High-speed, singie-LAB MAX 5000 EPLD t PD as fast as 10 ns Counter frequencies up to 125 MHz Pipelined data rates up to 83 MHz 32 individually configurable macrocells 64 shareable expander product terms "expanders" allowing 68

EPM5128LC

Abstract: epm5128jc MPM5128LC
Contextual Info: MPLDs Mask-Programmed Logic Devices Data Sheet September 1991, ver. 1 □ □ □ Features □ □ □ □ □ □ General Description Masked versions of EPLD designs Reduced cost for large-volume applications Available for EP1810, EPM5032, EPM5064, EPM5128, EPM5130,

Contextual Info: EPM5032 EPLD □ Features □ □ □ □ General Description High-speed 28-pin DIP, J-lead, or SOIC single-LAB MAX 5000 EPLD Combinatorial speeds with tPD = 15 ns Counter frequencies up to 76 MHz Pipelined data rates up to 83 MHz 32 individually configurable macrocells

Contextual Info: EPM5016 to EPM5032 MAX EPLDs with a Single LAB Data Sheet January 1990 Product Summary □ □ □ □ □ □ □ □ □ Single-LAB CMOS EPLDs offering a consistent design solution across a broad range of speed and density requirem ents 15-ns combinatorial delays

program EPM5032

Abstract: MSI MS-5
Contextual Info: EPM5032 EPLD Features • ■ ■ ■ ■ High-speed, single-LAB MAX 5000 EPLD t PD as fast as 10 ns Counter frequencies up to 125 MHz Pipelined data rates up to 83 MHz 32 individually configurable macrocells 64 shareable expander product terms "expanders" allowing 68

7400series

Abstract: cmos logic 7400 series 7400 family TTL 7400-series EPM5016
Contextual Info: The Complete Industry-Standard Programm able Logic Family MAX 5000 EPLDs 384 EPM5192 tpp = 25 ns - C/> 0> .c o 3 08 EPM5128 tpp —25 ns 256 CO Q. A EPM5130 tpp —25 ns O / ca> D EPM5064, tPD = 25 ns 128 ▲ EPM5032, tPD = 15 ns 64 ▲ EPM5016, tPD = 15 ns

Contextual Info: MPM5032 MPLD Features □ □ □ □ □ □ □ □ General Description CM OS, M ask-Program m ed Logic D evice M PLD capable of implementing high-density custom logic functions High-volume replacement for EPM5032 EPLD designs Zero-power operation (typically 8 (iA standby)

EPM5130

Abstract: J-Lead, EPM5128 APPLICATION NOTE ALTERA MAX 5000 MAX5000 macrocell Altera EPM5128 EPM5064-1
Contextual Info: MAX 5000 M M M & Programmable Logic Device Family , J a n u a r y 1 9 9 8 . v e r. 4 F e a tu re s . D a ta S h e e t m • ■ ■ Table 1. MAX5000 Device Features EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Usable gates 600 1,250 2,500 2,500 3,750 Macrocells

50321

Contextual Info: EPM5032 EPLD Features □ □ □ □ □ □ ü H ig h -s p e e d 28 -p in DIP, J-lead, o r SOIC single-LA B MAX 5 0 0 0 EPLD C o m b in a to ria l s p e e d s w ith tPD = 15 ns C o u n t e r f re q u en c ies u p to 76 M H z P ipelined d a ta rates u p to 8 3 M H z

MSI MS-5

Contextual Info: EPM 5032 EPLD Features H • ■ ■ ■ ■ High-speed, single-LAB MAX 5000 EPLD t PD as fast as 10 ns Counter frequencies up to 125 MHz Pipelined data rates up to 83 MHz 32 individually configurable macrocells 64 shareable expander product terms "expanders" allowing 68

EPM5032

Abstract: program EPM5032 ple3-12a PLS-MAX PLDS-MAX altera LP4 74HC
Contextual Info: 32 MACROCELL h igh d e n s it y m ax e p ld P P M c r m u u u c FEATURES G EN E R A L D E SC R IP T IO N • Erasable, User-Configurable, High-Density replacement for TTL and 74HC logic. • Advanced 0.8 micron CMOS EPROM technology. • High speed tpd = 20ns and 83MHz clock

EPM5130

Abstract: EPM5192 EPM5064 EPM5032 EPM5032-15 EPM5064-1 EPM5128 ALTERA MAX 5000 EPM5064-2 ALTERA MAX 5000 programming
Contextual Info: MAX 5000 Programmable Logic Device Family June 1996, ver. 3 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

EPM5032A

Abstract: MSI MS-5 EPM5032-25 EPM5032 EPM5032-15 EPM5032 max 0H22D ns288
Contextual Info: EPM 5032 EPLD Features 0005 XVIAI High-speed, single-LAB M AX 5000 EPLD t PD as fast as 10 ns Counter frequencies up to 125 MHz Pipelined data rates up to 83 MHz 32 individually configurable macrocells 64 shareable expander product terms "expanders" allowing 68

EPM5130

Contextual Info: MAX 5000 Programmable Logic Device Family January 1998. ver. 4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array M atrix MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

EPM5128GM

Abstract: EPM5128GC EPM5128JC EPM5032DC EPM5128GC-1 epm5130qc EPM5130QC-2 EPM5032DC-20 EPM5032DC-15 EPM5130LC
Contextual Info: MAX 5000 Programmable Logic Device Family May 1999, ver. 5 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

adv9606

Abstract: EPM5130 EPM5064 ALTERA MAX 5000 EPM5032 max EPM5192 micron EPM5032 EPM5128
Contextual Info: CUSTOMER ADVISORY MAX 5000 TRANSITION SCHEDULE UPDATE In PCN 9407, Altera announced the transition of its MAX 5000 family from a 0.8-micron process to a 0.65-micron process and provided reliability data at that time. This change improves AlteraÕs ability to support the MAX 5000 family on a long-term basis. No changes

epm5130

Abstract: EPM5064 PQFP 176 J-Lead tnand 4536C EPM5032 max ALTERA MAX 5000 programming epm5032 max5000 EPM5128 APPLICATION NOTE
Contextual Info: MAX 5000 Programmable Logic Device Family Data Sheet Features. • ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays Complete family of high-performance, erasable CMOS EPROM

EPM5130

Abstract: max 5000
Contextual Info: MAX 5000 Programmable Logic Device Family May 1999, ver. 5 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

Contextual Info: MAX 5000 Programmable Logic Device Family June 1996, ver. 3 F e a tu re s. Data Sheet * • ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array Matrix MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

EPM5130

Abstract: L9116 EPM5064 EPM5032 EPM5032-15 EPM5064-1 EPM5128 EPM5192 epm5130g EPM5032-2
Contextual Info: MAX 5000 Programmable Logic Device Family June 1996, ver. 3 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

Contextual Info: MAX 5000 Programmable Logic Device Family January 1998, ver. 4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX® 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

epm5064

Abstract: EPM5130 EPM5128 APPLICATION NOTE CERAMIC CHIP CARRIER LCC 68 socket EPM5130 adapter
Contextual Info: MAX 5000 Programmable Logic Device Family May 1999, ver. 5 F e a tu r e s. Data Sheet * • ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array Matrix MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

EPM5130

Abstract: program EPM5032
Contextual Info: MAX 5000 M UM Programmable Logic Device Family May 1999. ver. Features. • ■ ■ ■ ■ ■ ■ ■ Advanced M ultiple A rray M atriX MAX® 5000 architecture com bining speed and ease-of-use of PAL devices w ith the density of program m able gate arrays

program EPM5032

Abstract: EPLD 5032 VC 5032
Contextual Info: EPM 5032 EPLD Features □ H ig h -sp eed , sin gle-L A B M A X 5000 E PL D t PD as fast as 15 ns C ou n ter frequ en cies up to 77 M H z P ip elined d ata rates up to 83 M H z 32 in d iv id u ally con fig u rab le m acrocells 64 sh areab le exp an d er p ro d u ct term s "e x p a n d e rs " allo w in g 68