EP910 PROGRAMMER Search Results

Contextual Info: m ft i m intpl ¡PLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns ■ Extensive Software and Programming Support via Intel and Third-Party Tools

intel PLD

Abstract: INTEL PLD910 PLD910-25
Contextual Info: in tj ÌPLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • tpD 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns ■ Ice = 150 mA Max @ 1 MHz ■ Programmable Low-Power Option for “Standby” Operation; 60 /¿A Typ. in

85C090

Abstract: N85C090-20
Contextual Info: in te i 85C090 24-MACROCELL CHMOS jaPLD • Function, Pin, and JEDEC Compatible with 5C090, EP900, EP910 and EP930 ■ Extensive Software and Programming Support via Intel and Third-Party Tools ■ tpo 15 ns, 66 MHz w/Feedback, Clock to Output 9 ns ■ 1-Micron CHMOS HIE* EPROM

Signal Path Designer

Contextual Info: Classic EPLD Family J a n u a ry 1998. ver. Features Data Sheet 4 * • ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features EP610 EP610I EP910 EP910I EP1810 300 450 900 Macrocells 16 24 48 Maximum user I/O pins 22 38 64 Feature Usable gates Altera Corporation

dpld910

Abstract: pld910 IPLD910-25 DPLD910-15 adf simu 5C090 tcl eprom intel PLD INTEL PLD910 adf compiler
Contextual Info: i n t j . ÌPLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP91QA, 85C090 and 5C090 m tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns • Ice = 150 mA Max @ 1 MHz ■ Programmable Low-Power Option for “Standby” Operation; 60 ju.A Typ. in

npld910-25

Abstract: 85C090 P85C090 p85c090-25 PLD910-15 TN85C090-25 INTEL PLD910 npld intel PLD NPLD910-12
Contextual Info: INTEL CORP MEMORY/PL] / SbE J> m 4 A 2 b l 7 b 0 0 7 7 5 1 7 514 • I T L 2 ir r te l. P W io - 1 ^ - 0 ^ ¡PLD910/85C090 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 Extensive Software and Programming

MDPLD910-20

Contextual Info: A P M Ä N K D ü O M F [^ [M A T rO ® M in t e i MILITARY ÌPLD910 24-MACROCELL CHMOS jaPLD Function, Pin, and JEDEC Compatible with M5C090, EP900, EP910 and EP930 • Extensive Software and Programming Support via Intel and Third-Party Tools tpo 20 ns, 40 MHz w/Feedback, Clock

ep910 programmer

Abstract: EP610 EP610-15 48-macrocell EP1810 EP610-20 EP610-25 EP610-30 EP910 ep610 application
Contextual Info: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements

ep910 programmer

Abstract: EP610 programmer EPLD EP610-25 EP1810 EP610-15 EP610-20 EP610-30 EP910 K925
Contextual Info: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements

EP910dm

Abstract: EP910PC-30 EP910DC-40 EP1810LC-35 EP1810LC-20 EP610PC-15 Programming EP610DI-30 EP910JI-35 EP610IDC25 EP610SC-15
Contextual Info: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements

Contextual Info: Classic EPLD Family January 1998, ver. 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements

programming epm7032

Abstract: Altera EP1800 altera EP600 22V10E EP610 "pin compatible" ALTERA MAX 5000 programming EP224 PLMJ7000-84 ep910 programmer EPX740
Contextual Info: Altera Programming Hardware Data Sheet March 1995, ver. 2 General Description Altera offers a variety of hardware to program and configure Altera devices. The following products are available: • ■ ■ ■ ■ Altera Stand-Alone Programmer Logic Programmer card

Altera EP1810

Abstract: EP1810 EP600I EP610 EP610-15 EP610-20 EP910 EP610 "pin compatible"
Contextual Info: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of up to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements

ep600i

Abstract: EP1800I EP610ILI-12 altera ep610 altera EP1810 EP1800 altera ep900i
Contextual Info: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of up to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements

PLMG7192-160

Abstract: PLMJ1213 Altera Programming Hardware plmxxxx ALTERA MAX 5000 programming ALTERA PLMJ1213 PLMR9000-208 programming epm7032 PLMJ7000-68 EP610 "pin compatible"
Contextual Info: Altera Programming Hardware June 1996, ver. 3 General Description Data Sheet Altera offers a variety of hardware to program and configure Altera devices. For conventional device programming, in-system programming, and in-circuit reconfiguration, designers can choose from the hardware

PLMJ1213

Abstract: ALTERA MAX 5000 programming ep910 programmer PLMJ7000-68 PLMG9000-280 plmxxxx PLAD3-12 PLMD5032A PLMG5130A PLMG7192-160
Contextual Info: Altera Programming Hardware June 1996, ver. 3 General Description Data Sheet Altera offers a variety of hardware to program and configure Altera devices. For conventional device programming, in-system programming, and in-circuit reconfiguration, designers can choose from the hardware

Signal Path Designer

Abstract: altera ep910i
Contextual Info: Classic EPLD Family M ay 1999 ver. ;> Features D ata S h e e t • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements

J1213

Abstract: ep910 programmer T1064S 132 pin PGA socket
Contextual Info: Altera Programming Hardware Ju n e 1996. ver. 3 General _ . . . UcSlfliptllin Data Sheet A ltera o ffers a v a rie ty o f h a rd w a re to p ro g ra m a n d c o n fig u re A ltera devices. F or c o n v e n tio n a l d e v ic e p ro g ra m m in g , in -sy ste m p ro g ra m m in g ,

Signal Path Designer

Contextual Info: Classic EPLD Family M ay 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogram m ing w ith non-volatile EPROM configuration elements

Altera LP5

Abstract: Altera EP1800 logicaps schematic capture EPM5016 EP1810 PLEj1810 PLDS-MAX ep330 EPS448D 02D-00209
Contextual Info: AN Ü □ !^ V a \ Product Selection Guide Data Sheet September 1991, ver. 2 In t r o d u c t io n P r°d u c t Selection G uid e summarizes the range of products available from Altera: U □ U Ü U U U General-purpose E P L D s Function-specific E P L D s

Date Code Formats Altera EPF10K

Abstract: ep22v10 5962-9061102XA 5962-8854901xa 8686401LA 5962-8686401LA lift controller in vhdl ALTERA PART MARKING EPM7160 EPX780 transistor b2020
Contextual Info: Introduction Contents March 1995 Introduction The PLD Advantages of Altera

PLE3-12

Abstract: PLE3-12 EP1810 EP900I PLE3-12A EP1800I
Contextual Info: Glossary June 1996 A Altera Hardware Description Language AHDL Altera’s design entry language. AHDL is a highlevel, modular language that is completely integrated into MAX+PLUS II. You can create AHDL Text Design Files (.tdf) with the MAX+PLUS II Text Editor or any standard text

EP1800I

Abstract: PLE3-12 EP1810 orcad schematic symbols library vhdl code direct digital synthesizer ep910 ieee
Contextual Info: Glossary February 1998 A Altera Consultants Alliance Program ACAP An alliance created to provide expert design assistance to users of Altera programmable logic devices (PLDs). ACAPSM consultants provide their expertise and services to designers. Altera Hardware Description Language (AHDL)

altera jed to pof convert

Abstract: EP1810 jedec EPM memory epx780 ep330
Contextual Info: / a \| l l l" £ Glossary March 1995 A Altera Hardware Description Language AHDL A ltera's design entry language. AH DL is com pletely integrated into M A X +P L U S II, and allows the designer to enter and edit Text Design Files (.tdf) with the M A X +PLU S II Text