ELLS 110 Search Results

ssl 110 sn

Abstract: sda 9205 DG533 ELLS 110
Contextual Info: bSE T> m ÖS3SbüS DG53351 130 « S I E G SIEM ENS SIEMENS AKT IENG ES ELLS CH AF Triple 8-Bit Analog-to-Digital Converter SDA 9205 CMOS 1C Preliminary Data Features • Three equivalent CMOS A/D converters on chip • 30-MHz sample rate • 8-bit resolution

CY7C375

Abstract: DL086
Contextual Info: fax id: 6140 CY7C375Î CYPRESS UltraLogic 128-Macrocell Flash CPLD Features Functional Description 128 m a cro c ells in eig h t logic blocks The C Y 7 C 3 75i is an In-System R eprogram m able C om plex P rogram m able Logic Device C PLD and is pa rt of the

CY37128

Abstract: CY37128V
Contextual Info: CY37128V PRELIMINARY i k v / kv, UltraLogicT M 3.3V 128-Macrocell ISR CLPD Features — tpD = ns — ts = 5.5 ns • 128 m a cro c ells in eig h t logic blocks — tc o = 6.5 ns • 3.3V In-S ystem R eprog ram m ab le™ IS R ™ • P ro d uct-term clocking

CY37128P160-125AC

Abstract: cpld internal CY3600 CY37128P100-167AC Ultra37128 CY37128P84-125JI
Contextual Info: fax id: 6146 : : M : : IP *: ; M : : Ultra37128 .PRELIMINARY W CYPRESS UltraLogic 128-Macrocell ISR™ CPLD Features High speed f|\/lAX = 167 M Hz • 128 m a cro c ells in eig h t logic blocks — t PD = 6.5 ns • In-S ystem R e p ro g ra m m ab le IS R ™

ES0406

Abstract: r00nF A6151 TDA615 6151X sc 6700
Contextual Info: bSE D • fi235bD5 0 0 5 3 7 ^ 7T4 « S I E G SIEM EN S_ _ SIEMENS AKTIENGES ELLS CHAF S a t e l l i t e - V i d e o IC TDA6151X Bipolar 1C Preliminary Data Features • G a in adjustable for different FM -deviations • V id e o buffer and sp ecial baseband output for the sound

Contextual Info: fax id: 6136 CY7C371 i ^C YPR ESS UltraLogic 32-Macrocell Flash CPLD Features sig ne d to bring the ease of use and high pe rfo rm an ce o f the 22V 10, as w ell as PCI Local Bus S pe cifica tion sup po rt, to high -den sity CPLDs. • 32 m a cro c ells in tw o logic blocks

Contextual Info: fax id: 6136 PRELIMINARY CY7C371 i UltraLogic 32-Macrocell Flash CPLD Features sig ne d to bring the ease of use and high pe rfo rm an ce o f the 22V 10, as w ell as PCI Local Bus S pe cifica tion sup po rt, to high -den sity CPLDs. • 32 m a cro c ells in tw o logic blocks

Contextual Info: fax id: 6136 CY7C371 i ^C YPR ESS UltraLogic 32-Macrocell Flash CPLD Features sig ne d to bring the ease of use and high pe rfo rm an ce o f the 22V 10, as w ell as PCI Local Bus S pe cifica tion sup po rt, to high -den sity CPLDs. • 32 m a cro c ells in tw o logic blocks

lem la 100-P

Abstract: E1101
Contextual Info: Ultra37128 P R E U M IN A m UltraLogic 128-Macrocell ISR™ CPLD Features — t co = 4.5 ns P ro d uct-term clo ckin g • 128 m a cro c ells in eig h t logic blocks IEEE1149.1 JTAG b o u n d a ry scan • In-S ystem R e p ro g ra m m ab le IS R ™

T1119

Contextual Info: ^^W ^C Y P R K S S Ultra37256V preliminary UltraLogic 3.3V 256-Macrocell ISR™ CPLD Features — t PD = 12 ns — ts = 7 ns • 256 m a cro c ells in sixteen log ic blocks — t co = 6.5 ns • 3.3 V In -S ystem R ep ro g ram m ab le™ IS R ™ • P ro d uct-term clo ckin g

Contextual Info: fax id: 6140 CY7C375Ì UltraLogic 128-Macrocell Flash CPLD • A v ailab le in 160-p in TQFP, CQFP, and PG A p ackag es Features Functional Description • 128 m a cro c ells in eig h t logic blocks • 128 I/O pins T he C Y 7 C 3 75i is an In-System R eprogram m able C om plex

CY37256

Abstract: CY37256V
Contextual Info: CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD F eatu res — tPD = 12 ns — ts = 7.0 ns • 256 m a cro c ells in sixteen logic blocks — tc o = 6.0 ns • 3.3V In-S ystem R eprog ram m ab le™ IS R ™ • P ro d uct-term clocking — JT A G -co m p liant o n -b o a rd p ro gram m in g

y373

Abstract: CY37384
Contextual Info: ^ ^ ^ PRELIMINARY CYPRKSS CY37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — t co = 6.0 ns • 384 m a cro c ells in 24 logic blocks • P ro d uct-term clo ckin g • In-S ystem R e p ro g ra m m ab le ™ IS R ™ • IE E E 1149.1 JTAG b o u n d a ry scan

l11J

Abstract: CY3600 cpld internal
Contextual Info: fax id: 6147 ÆÊ F T V f S T “ ¡T * &*• risaliiJF ;UI Flmßbö PRELIMINARY Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™ CPLD Features • High speed — f MAX = 125 M Hz • 128 m a cro c ells in eig h t log ic blocks — t PD = 10 ns • 3 .3 V In-S ystem R e p ro g ra m m ab le IS R ™

TAG 2,5 200

Abstract: 1AAA CY37192 CY37192V
Contextual Info: CY37192 UltraLogic 192-Macrocell ISR™ CPLD • P ro d uct-term clocking Features • IEEE 1149.1 JTAG b o u n d a ry scan • 192 m a cro c ells in tw e lv e logic blocks • P ro g ram m a b le slew rate co n tro l on ind ividu al l/O s • In-S ystem R ep ro g ra m m ab le ™ IS R ™ including:

CY37384

Abstract: tms 0119 256-pin Plastic BGA 17 x 17
Contextual Info: = m m m !Æ '^ r ^ r : c Q P R £ U M lm fíY CY37384 i í.-.-.-.í k v / k., UltraLogic 384-Macrocell ISR™ CPLD Features — ts = 5.5 ns — tc o = 6 ns • 384 m a cro c ells in 24 logic blo cks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™

CY3600

Contextual Info: fax id: 6149 SS i^K JS f r i s a l i i J F ; U FTV fST “ ¿ N &*• I F l m c b PRELIMINARY Ultra37256V t i UltraLogic 256-Macrocell 3.3V ISR™ CPLD Features • Up to 192 1/Os — plus 5 d ed icated inp u ts including 4 clo ck inputs • 256 m a cro c ells in six te en logic blocks

Contextual Info: BAGM 024B S p e c ific a tio n C ells Per Unit V oltage Per Unit 12 C ap acity 2 6.0A h@ 20hr-rate to 1 75V p er cell @ 25DC W eig ht A pp ro x. 8.6 Kg M ax. D isch arg e C u rre n t 260 A 5 sec In tern a l R esistance A pp ro x. 10 m ii O p erating Tem perature Range

Contextual Info: PREUM INAm Ultra37512 UltraLogic 512-Macrocell ISR™ CPLD — t co = 6 n s Features P ro d uct-term clo ckin g • 512 m a cro c ells in 32 logic blocks IEEE1149.1 JTAG b o u n d a ry scan • In-S ystem R e p ro g ra m m ab le ™ IS R ™ P ro g ram m a b le slew rate co n tro l on ind ividu al l/O s

General electric SCR

Abstract: c701 scr scr 151 C380 SCR 2000 SCR general electric scr welding general electric c350 A430 C350
Contextual Info: HEAT EXCHANGER MODULES for HIGH CURRENT R E C T IFIE R S & SCRs G 6 /G 14 /G 1 5 G 9 /G 1 0 /3 N 2 2 1 /3 N 2 2 2 CELL D ATA 180° C O N D U C T IO N , L IQ U ID C O O LE D A T 40°C 1 G PM C E L L NO. M A X . V O LT S PER C E L L S IN G LE SURGE AMPS A 390

Contextual Info: M ITEL £? SEMI CONDUCTOR D | fe.2tH370 MITEL* >, y. 12E □ Q0 5G ? fl 0 g ISO-CMOS ST-BUS FAMILY MT8970 Digital Line Interface Circuit 7 T-lS-y-S -o v ._ f/t •»> A* X A -■'•»S •». s? •* « ✓ « « « '» W A V « . « *%• T v D E C E M B E R 1987

Contextual Info: Order this data sheet by H4C/D MOTOROLA H SEMICONDUCTOR “ TECHNICAL DATA Advance Information H4C SERIES CMOS ARRAYS and the CDA™ ARCHITECTURE H IG H P ER FO R M A NC E T R IP L E LAYER M ETAL S U B -M IC R O N CMOS ARRAYS The s u b -m ic ro n H 4C S e rie s ’ " CM OS gate array fa m ily and th e new

transistor c103m

Abstract: C103M c105m W41l c105m TRANSISTOR c103m TRANSISTOR C103M equivalent 54175 4013 bt CMOS Sc 54155
Contextual Info: TGC100M MILITARY SERIES 1/im CMOS GATE ARRAYS Release 2.0, APRIL 1989 Fully Characterized for Military Applications — Product Fully Compliant with the Requirements of M IL-STD-883 Paragraph 1.2.1 Is Available — Production Processing Is in Accordance with the General Requirements of

Contextual Info: dUy 000975 D E VI C E SPECIFIC f ^ ?:> APPLIED MICRO CIRCUITS CORPORATION f t m c Q6000A SERIES CMOS LOGIC ARRAYS FEATURES TECHNOLOGY Q 60 00A Series arrays feature 1.8-m icron silico n -g a te CM O S with tw o-level m etalization, offerin g high p e rfo rm a n ce and up to