EF50 Search Results

Mullard ef50

Abstract: EF50 G3JL Mullard
Contextual Info: EF50 SH O R T W A VE R.F. PEN TO D E Single-ended R.F. pentode, fully controlled by voltages o f 0 to — 6V or 0 to — 55V according to the circuit used. HEATER Vh 6 .3 V I h 0 .3 A 0 .0 0 7 2 *4 8 .3 5 .2 uu? uui uuf uuF CAPACITANCES V a lv e c o l d °a -g l

EF50

Contextual Info: page 1 2 3 EF50 sheet 1 2 FP date 1953.11.11 1953.11.11 1999.06.20

EF50

Contextual Info: page 1 2 3 EF50 sheet 1 2 FP date 1953.04.04 1953.04.04 1999.06.28

EF50

Contextual Info: PHILIPS EF50 PENTODE for use as wide band and measuring amplifier PENTHODE pour utilisation comme amplificatrice à large bande et de mesure PENTODE zur Verwendung als Breitband- und Messver­ stärker Heating: indirect by A.C. or D.C.; parallel supply Chauffage: indirect par C.A. ou C.C.;

Mullard ef50

Abstract: Mullard EF50
Contextual Info: R.F. PENTODE EF50 S ingle-ended r .f . pentode, fu lly c o n tro lle d b y vo ltages o f 0 to — 6V o r 0 to — 5 5 V a c c o rd in g to th e c ir c u it used. H EA TER Suitab le fo r series o r parallel o p e ra tio n a.c. o r d.c. Vh 6.3 Ih 300 V mA C A P A C IT A N C E S

f50z

Contextual Info: GEC PLESSEY SEMICONDS IE D •! 37bfl522 0GQÔS12 T « P L S B A SPLESSEY e m ic o n d u c to rs l~ - 5 ê - 0 1 EF50/EF50Z 5V MICROPOWER PRECISION REFERENCES T h e EF50 and R EF50Z are m icropow er integrated circuits using the bandgap principle to provide a precise

Contextual Info: Silicon Rectifier Formosa MS EF501G THRU EF505G List List. 1 Package outline. 2 Features. 2

6206a

Abstract: K-Line transceiver w1p 84 st10f2xx sigma asc 333 24 pin K-line ST10F276E W1P 59 st10 Bootstrap st10273e
Contextual Info: ST10F276E 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM Datasheet − production data Features • ■ ■ ■ ■ ■ Highly performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD48288209, 48288218, 48288236 288M-BIT Low Latency DRAM Common I/O Description The μPD48288209 is a 33,554,432-word by 9 bit, the μPD48288218 is a 16,777,216 word by 18 bit and the μPD48288236 is a 8,388,608 word by 36 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology

4DP20

Abstract: STK 5333 MCA051 C164 C164CM C164CM-4E C164CM-4R C164SM-4R C166 C167
Contextual Info: U s e r ’ s M a n u a l , V 1. 0 , F e b . 2 00 2 C164CM/SM 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . Edition 2002-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany Infineon Technologies AG 2002.

C164CL

Abstract: C164SI cisc architecture in 8051 C164CI-8R C164CL-8R C164SI-8R C166 C164 C164CI C164SL-8R
Contextual Info: U s e r ’ s M a n u a l , V 3. 1 , F e b . 2 00 2 C164CI/CL C164SI/SL 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . Edition 2002-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany

STK 5333

Abstract: siemens C167 C164CL-8rm C164 C164 instruction set C164CL Transistor hall sq C164SI C16x C167 siemens
Contextual Info: www.infineon.com Microcontrollers C166 Family 16-Bit Single-Chip Microcontroller C164 User’s Manual 1999-09 V 2.0 Edition 1999-09 Published by Infineon Technologies AG, St.-Martin-Strasse 53 D-81541 München Infineon Technologies AG 1999. All Rights Reserved.

st10f276 jtag

Abstract: w1p 59 ST10F276 st10 Bootstrap EF52 transistor w2P w1p 83 W1P 76 transistor LQFP144 ST10
Contextual Info: ST10F276 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM Features • ■ ■ ■ ■ ■ Highly performant 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

ecc84

Abstract: embedded powerpc 460 AMCC 460, DATE CODE 440GR E800 EF40 PPC440 PPC440GR PPC440GR-3JB667CZ epbga
Contextual Info: Part Number 440GR Revision 1.19 – May 07, 2008 440GR Preliminary Data Sheet PowerPC 440GR Embedded Processor Features • PowerPC 440 processor core operating up to 667MHz with 32KB I-cache and D-cache with parity checking. • Two Ethernet 10/100Mbps half- or full-duplex

spi c sorce code for 8051

Abstract: STK 419 140 STK 419 130 C164CI C164CI-8EM C166 C167 C164CI-8EM CA
Contextual Info: C164CI ht User’s Manual 08.97 Version 1.0 tp :/ Se /ww m w ic .s on ie du me ct ns or .d / e/ 16-Bit CMOS Single-Chip Microcontrollers Edition 08.97 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München Siemens AG 1997.

C100H

Abstract: PIN DIAGRAM of st10f280 EE30h st10 Bootstrap BUT16
Contextual Info: ST10F280 16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM PRODUCT PREVIEW • ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION - ON-CHIP PLL. - DIRECT OR PRESCALED CLOCK INPUT. ■ UP TO 143 GENERAL PURPOSE I/O LINES - INDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIAL FUNCTION.

embedded powerpc 460

Contextual Info: Part Number 440GR Revision 1.17 – January 07, 2008 440GR Preliminary Data Sheet PowerPC 440GR Embedded Processor Features • PowerPC 440 processor core operating up to 667MHz with 32KB I-cache and D-cache with parity checking. • Two Ethernet 10/100Mbps half- or full-duplex

amcc ppc440ep

Abstract: AMCC DATE CODE MARKING amcc 440ep PPC440EP Emccd PPC440 epbga 304 AMCC 460, DATE CODE embedded powerpc 460 Philips DCR 5000
Contextual Info: Part Number 440EP Revision 1.24 – July 19, 2006 440EP Preliminary Data Sheet Power PC 440EP Embedded Processor Features • PowerPC 440 processor core operating up to 667MHz with 32KB I-cache and D-cache with parity checking. • Selectable processor:bus clock ratios of N:1, N:2.

ansi y32

Abstract: ag30 transistor transistor z 0607 b09 n03 transistor
Contextual Info: Part Number 440GRx Revision 1.03 – May 30, 2006 440GRx Preliminary Data Sheet PowerPC 440GRx Embedded Processor Features • PowerPC 440 processor operating up to 667MHz with 32KB I-cache and D-cache with parity checking • 16KB of on-chip SRAM • Selectable processor:bus clock ratios of N:1, N:2

ST10R201

Abstract: ST10F272 TQFP144 DIMENSION M29F400 PQFP144 ST10 ST10F269 ST10F272B ST10F272E TQFP144
Contextual Info: ST10F272B ST10F272E 16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM Features • ■ ■ 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit multiplication, 40-bit accumulator

STK 411-550 E

Abstract: stk power amplifiers 411-550 UM0404 st10 Bootstrap datasheet STK 411-550 E 221-550 st10f276 jtag DIS12 ST10F276 CAN bit timing ST10
Contextual Info: UM0404 User manual ST10F276 Introduction This manual describes the functionality of the ST10F276 device. An architectural overview describes the CPU performance, the on-chip system resources, the on-chip clock generator, the on-chip peripheral blocks and the protected bits.

Contextual Info: SAW Filters for Cellular Telephone SAW Filters for Cellular Telephone For RF-Stage EFCH111MM111 SAW Filter for Cellular Telephone which incorporates highly-precise interdigited electrodes achieves low insertion loss, high selectivity. Thus the filter has wide

line following robot diagram 8051

Abstract: sae j1850 pwm ford peugeot infineon C166 reliability report Infineon C515C 81C91 PROTOCOL abs bosch hardware examples renault Bosch ABS module 5.3
Contextual Info: Application Note, V 1.0, Feb. 2004 AP29000 CAN Co nnec tin g C1 66 a nd C5 00 Micr ocon tro l ler to CAN . Micr ocon tro l lers N e v e r s t o p t h i n k i n g . CAN Revision History: 2004-02 V 1.0 Previous Version: Page Subjects major changes since last revision

6414a

Abstract: st10 Bootstrap AN23 LQFP144 PQFP144 ST10 ST10F272E ST10F272M 3170B
Contextual Info: ST10F272M 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM Features • ■ ■ 16-bit CPU with DSP functions – 50ns instruction cycle time at 40 MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit multiplication, 40-bit accumulator – Enhanced boolean bit manipulations