EE00 Search Results

Contextual Info: T H IS C DR AWI NG IS U N P U B L IS H E D , CGPYRIGHT RELEASED BY TYCD ELECTRONICS C DR P DR A TI DN FDR ALL P U B L IC A T IO N RI GHT S LO G RESERVED, DIST REVISIONS DS P LTR B2 DATE DWN 09, AUG,'04 UG 05,D E E ,'0 8 KT DESCRIPTIO N REVISED EEN (EE00-0176-04)

Socket S1g1

Abstract: AMD Turion 64 Mobile Technology AM2 amd amd AM2 opteron pin package HTC B834 Socket S1g1 Processor Functional AMD SEMPRON 3000 socket 754 DIAGRAM SEMPRON Socket 754 AM2 31117 CMPXCHG16B
Contextual Info: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors Publication # 32559 Revision: 3.16 Issue Date: November 2009 2005-2009 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices,

6206a

Abstract: K-Line transceiver w1p 84 st10f2xx sigma asc 333 24 pin K-line ST10F276E W1P 59 st10 Bootstrap st10273e
Contextual Info: ST10F276E 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM Datasheet − production data Features • ■ ■ ■ ■ ■ Highly performance 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit MAC 16 x 16-bit

SA6954

Abstract: S29WS064N S29WS128N S29WS256N WS128N FFC00
Contextual Info: S29WSxxxN MirrorBit Flash Family S29WS256N, S29WS128N, S29WS064N 256/128/64 Megabit 16/8/4 M x 16-Bit CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory PRELIMINARY Distinctive Characteristics Architectural Advantages „ Single 1.8 volt read, program and erase (1.70 to

Contextual Info: SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual JANUARY 2008 SPRS462B SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual Literature Number: SPRS462B SEPTEMBER 2007 – Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date.

DFSDM

Abstract: SAM9M10 K 2141 AC97 ARM926EJ-S AT91SAM ISO7816 NBC 3111 hc 541 rfid reader id-20
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static

diode T35 12H

Abstract: ST10F269Z2Q6 ST10F269Q ST10F269Z2T3 PQFP144 ST10F269 TQFP144 diode t318 BB126 st10 Bootstrap
Contextual Info: ST10F269 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET • ■ 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM CAN1_RXD CAN1_TXD CAN1 CAN2_RXD CAN2_TXD CAN2 PEC Oscillator and PLL 16 Interrupt Controller

Contextual Info: TMS320C6454 Fixed-Point Digital Signal Processor SPRS311C – APRIL 2006 – REVISED MAY 2007 1 Features • • • • • • High-Performance Fixed-Point DSP C6454 – 1.39-, 1.17, and 1-ns Instruction Cycle Time – 720-MHz, 850-MHz, and 1-GHz Clock Rate

Contextual Info: TMS320C6455 Fixed-Point Digital Signal Processor www.ti.com SPRS276F – MAY 2005 – REVISED MARCH 2007 1 TMS320C6455 Fixed-Point Digital Signal Processor 1.1 Features • • • • • • • High-Performance Fixed-Point DSP C6455 – 1.39-, 1.17 and 1-ns Instruction Cycle Time

Contextual Info: TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com TMS320C6472 Fixed-Point Digital Signal Processor 1 Features • • • • • • • • • • • Congestion Control • IEEE 1149.6 Compliant I/Os – UTOPIA • UTOPIA Level 2 Slave ATM Controller

A00C

Contextual Info: TMS320C6454 Fixed-Point Digital Signal Processor SPRS311D – APRIL 2006 – REVISED OCTOBER 2007 1 Features • • • • • • High-Performance Fixed-Point DSP C6454 – 1.39-, 1.17, and 1-ns Instruction Cycle Time – 720-MHz, 850-MHz, and 1-GHz Clock Rate

Contextual Info: TMS320C6455 www.ti.com SPRS276M – MAY 2005 – REVISED MARCH 2012 TMS320C6455 Fixed-Point Digital Signal Processor Check for Samples: TMS320C6455 1 Features 12 • High-Performance Fixed-Point DSP C6455 – 1.39-, 1.17-, 1-, 0.83-ns Instruction Cycle Time

Contextual Info: IS24C02-3 m 2,048-BIT SERIAL ELECTRICALLY ERASABLE PROM i PRELIMINARY SEPTEMBER 1998 FEATURES • Low power CMOS Self-timed write cycle — Active current less than 2 mA — Maximum write cycle time of 10 ms — Standby current less than 8 fiA Endurance: 100,000 cycles per byte

Contextual Info: ISSI IS24C02_ 2,048-BIT SERIAL ELECTRICALLY ERASABLE PROM JANUARY 1998 FEATURES Endurance: 1, 000,000 cycles per byte 8-pin PDIP or SO IC packages Filtered inputs for noise suppression Low pow er CMOS — Active current less than 2 mA — Standby current less than 8 fiA

MCF51JM128 source code

Abstract: USB BootLoader for MCF51JM128 MCF51JM128 JM128 MC9S08* boot loader Freescale usb mcf51jm128 MC9S08JM60 c code example AN3561 MC9S08JM60 0x4E714EF9
Contextual Info: Freescale Semiconductor Application Note Document Number: AN3748 Rev. 0, 08/2008 USB BootLoader for MCF51JM128 by: Derek Liu Systems and Applications Engineering Microcontroller Solutions Group 1 Introduction MCF51JM128 is a member of the Freescale Flex JM

Contextual Info: ARM-based Embedded MPU SAM9G35 DATASHEET Description The SAM9G35 is a member of the Atmel series of 400 MHz ARM926EJ-S embedded MPUs that support high bandwidth communication and advanced user interfaces and are optimized for industrial applications such as building automation,

Contextual Info: AT91SAM ARM-based Embedded MPU SAM9263 Description The AT91SAM9263 32-bit microcontroller, based on the ARM926EJ-S processor, is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It also features two independent external memory buses, EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses prevent

AT91SAM9260B-CU

Abstract: AT91SAM9260B-QU application note SAM9260
Contextual Info: Features • 180 MHz ARM926EJ-S ARM Thumb® Processor – 8 KBytes Data Cache, 8 KBytes Instruction Cache, MMU • Memories • • • • – 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC

NAU8812

Abstract: AEC-Q100 TS16949 BTL POWER AMPLIFIER ic 4558 analog mems microphone NAU-8 microphone electret ecm 4f voltage of ic 4558 audio 0X049 mems mic
Contextual Info: NAU8812 Mono Audio Codec with Speaker Driver emPowerAudio 1. GENERAL DESCRIPTION The NAU8812 is a cost effective and low power wideband MONO audio CODEC. It is designed for voice telephony related applications. Functions include Automatic Level Control ALC with noise gate, PGA, standard audio interface

robot control

Abstract: C203 C209 SPRU121 TMS320 TMS320C203 TMS320C209 XDS510 TMS320F2XX
Contextual Info: TMS320C2xx User’s Guide Literature Number: SPRU127B Manufacturing Part Number: D412008-9761 revision A January 1997 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any

ATMEL 234

Abstract: how to derive sim 900 ARM926EJ-S AT91SAM ISO7816
Contextual Info: Features • Incorporates the ARM926EJ-S ARM Thumb® Processor • • • • • • • • • • – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 16-Kbyte Data Cache, 16-Kbyte Instruction Cache, Write Buffer

Fluke 19 Multimeter calibration manual

Abstract: FLUKE 87 iii service manual FLUKE 29 series II multimeter numeric water level indicator and working theory FLUKE 87 iii operating manual FLUKE 87 iii manual TL75-1 fluke FLUKE 75 series II multimeter FLUKE 187 manual FLUKE 87 manual
Contextual Info: 787 ProcessMeter Users Manual April 1997, Rev.3, 12/01 1997, 1898, 2000, 2001 Fluke Corporation, All rights reserved. Printed in U.S.A. All product names are trademarks of their respective companies. LIMITED WARRANTY & LIMITATION OF LIABILITY This Fluke product will be free from defects in material and workmanship for three years from the date of purchase. This

GPR circuit schematic diagram full

Abstract: DP43 T308 ST10F269-T6 ST*10f269-q3 m29F ST10F269-T3 TQFP144 f082h st10 Bootstrap
Contextual Info: ST10F269-T3 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM March 2003 FAIL-SAFE PROTECTION – PROGRAMMABLE WATCHDOG TIMER – OSCILLATOR WATCHDOG • ■ ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION – ON-CHIP PLL – DIRECT OR PRESCALED CLOCK INPUT

GPR circuit schematic diagram full

Abstract: ST10F269Z2q3 PQFP144 ST10 ST10F269 03 T48 regulator st10 Bootstrap
Contextual Info: ST10F269Z2Qx 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM PRELIMINARY DATA August 2002 • ■ 16 32 256K Byte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM PEC Oscillator and PLL CAN1_RXD CAN1_TXD