EDS2732AABJ Search Results
EDS2732AABJ Datasheets Context Search
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Contextual Info: DATA SHEET 256M bits SDRAM EDS2732AABJ-6B 8M words x 32 bits Pin Configurations • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V |
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EDS2732AABJ-6B 90-ball 166MHz cycles/64ms M01E0107 E0507E40 | |
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Contextual Info: DATA SHEET 256M bits SDRAM EDS2732AABJ-6B 8M words x 32 bits Description Pin Configurations The EDS2732AA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. |
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EDS2732AABJ-6B EDS2732AA 90-ball 166MHz M01E0107 E0507E20 | |
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Contextual Info: DATA SHEET 256M bits SDRAM EDS2732AABJ-6B 8M words x 32 bits Specifications Pin Configurations • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V |
Original |
EDS2732AABJ-6B 90-ball 166MHz cycles/64ms M01E0107 E0507E40 | |
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Contextual Info: DATA SHEET 256M bits SDRAM EDS2732AABJ-6B 8M words x 32 bits Description Pin Configurations The EDS2732AABJ is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. |
Original |
EDS2732AABJ-6B EDS2732AABJ 90-ball 166MHz M01E0107 E0507E30 | |
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Contextual Info: DATA SHEET 256M bits SDRAM EDS2732AABJ-75 8M words x 32 bits Description Pin Configurations The EDS2732AA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. |
Original |
EDS2732AABJ-75 EDS2732AA 90-ball 133MHz M01E0107 E0506E20 | |
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Contextual Info: DATA SHEET 256M bits SDRAM EDS2732AABJ-75 8M words x 32 bits Pin Configurations • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V |
Original |
EDS2732AABJ-75 90-ball 133MHz cycles/64ms M01E0107 E0506E40 | |
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Contextual Info: DATA SHEET 256M bits SDRAM EDS2732AABJ-75 8M words x 32 bits Specifications Pin Configurations • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V |
Original |
EDS2732AABJ-75 90-ball 133MHz cycles/64ms M01E0107 E0506E40 | |
|
Contextual Info: DATA SHEET 256M bits SDRAM EDS2732AABJ-75 8M words x 32 bits Description Pin Configurations The EDS2732AA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. |
Original |
EDS2732AABJ-75 EDS2732AA 90-ball 133MHz M01E0107 E0506E30 |