ECL F10K Search Results

F10014

Abstract: ECL Handbook F10506 ECL 200 F10105 f10107 F10-100 f10504
Contextual Info: F10014 ACTIVE TERMINATOR F10K VOLTAGE COMPENSATED ECL G E N ER A L D ESC R IP TIO N — The F10014 Is a voltage com pensated ECL circuit w h ich replaces discrete diode clam ping circuits at considerable reduction in cost, board space and power dissipation. It operates from the standard - 5 . 2 V ECL

CTR34

Abstract: FGE2000 BL33B DFI01 Fairchild ZN 1010 L1332 JKI02 ctr-34 SHR04 OAI43
Contextual Info: NATL SEMICOND -CMEnORY> □2E D | ts D iia b □□bi3n ? I FGE Series ECL Gate Arrays FAIRCHILD A Schlumberger Company Description FGE Series Features The FGE Series of ECL gate arrays are the fastest silicon gate arrays commercially available. These advanced ECL gate ar­

Fairchild ZN 1010

Abstract: GENERAL INSTRUMENT west 2500 ic ZN 415 FGE2000
Contextual Info: FGE Series ECL Gate Arrays PAIRCHIL.D A Schlum berc T'HO Qr>y 005596 January 1986 Description U/v\A m b The FGE Series of ECL gate arrays are the fastest silicon gate arrays com m ercially available. These advanced ECL gate arrays, ranging from 100 to 2840 equivalent gates, offer

Contextual Info: F10K VOLTAGE COMPENSATED ECL SERIES GENERAL DESCRIPTION — Fairchild F10K Series Emitter Coupled Logic ECL circuitsare high speed, low power logic elements intended for use in high speed systems such as central processors, memory controllers, peripheral equipment, instrumentation and digital communication systems.

TR20X3

Abstract: DFI01 OR02D
Contextual Info: December 1989 FGA S eries A S PE C T- ECL G ate A rrays General Description The FGA Series is a new generation of ECL gate arrays based on National’s ASPECT process. These advanced ECL gate arrays, ranging from 200 to over 30,000 equiva­ lent gates, offer typical internal propagation delays of

FGE0500

Abstract: FGE2000 FGE2500 F100K ECL 300 series and design guide Fairchild 100K series ECL Fairchild ZN 1010 1240 picosecond la 4440 LA 4440 circuit diagram PS-1050
Contextual Info: FGE Series ECL Gate Arrays F A IR C H IL D A Schlumberc J/n A 005596 January 1986 n Description 0r>y ^ Gate Array Division FiC The FGE Series of ECL gate arrays are the fastest silicon gate arrays commercially available. These advanced ECL gate arrays, ranging from 100 to 2840 equivalent gates, offer

AK 1230

Contextual Info: F10125 . F10525 QUAD ECL TO TTL TRANSLATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION — The F10125 and F10525 are Quad Translators for converting F10K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or as a differential receiver. An Internal reference voltage

Contextual Info: F10125 • F10525 ^ QUAD ECL TO TTL TRANSLATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION — The F10125 and F10525 are Quad Translators fo r converting F10K logic levels to TTL logic levels. D ifferential inputs allow each c irc u it to be used as an inverting, non-inverting or as a d iffe re n tia l receiver. An Internal reference voltage

a2c33

Contextual Info: ECL ISOPLANAR MEMORY F10411 256x1—BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION - The F10411 is a low voltage 256-bit Read/Write Ran­ dom Access Memory, organized 256 words by one bit. It has a 20 ns typical access time

HA 1370 schematics

Abstract: CMOS XNOR XOR NAND2 NAND3 ic ttl and not xor nor xnor or MICRON POWER RESISTOR 2W ECL IC NAND
Contextual Info: PRELIMINARY Semiconductor December 1990 NGM Series ABiC BiCMOS/ECL Gate Arrays General Description Features The NGM Series is a new family of mixed ECL and BiCMOS gale arrays based on National’s revolutionary 0.8 micron drawn ABiC BiCMOS process. The NGM Series is the first

clcc 68

Abstract: CLCC 44 Fairchild 100K series ECL CPGA routing CLCC 24 layout CERAMIC LEADLESS CHIP CARRIER LCC 44 CERAMIC leaded CHIP CARRIER CLCC 68 CPGA132 CPGA CLCC 84
Contextual Info: Gate Array Products FAIRCHILD A Schlum berger Com pany First/Second Q uarter 1986 Gate Array Division Fairchild Gate Array Division offers com plete in-house design and production capabilities for high perform ance ECL and CMOS gate arrays. Featured with all Fairchild ECL gate arrays are speed/power

eel -16-2005

Abstract: schmitt trigger ecl F10125 F10525 Scans-0017359
Contextual Info: / F10125 • F10525 J Q U A D ECL T O T T L T R A N S LA T O R F10K V O LT A G E C O M P E N S A T E D ECL D E SC R IPTIO N — The F10125 and F10525 are Quad Translators fo r converting F10K logic levels to TTL logic levels. D ifferential inputs allow each circu it to be used as an

F10410

Contextual Info: ECL ISOPLANAR MEMORY F10410 256xl-BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D ESC R IPTIO N - The F10410 is a 2 5 6 -b it Read/W rite Random Access Mem­ ory, organized 256 w ords by one b it. It has ty p ic a l access tim e o f 18 ns and is designed

F10410

Abstract: F10410DC F10405 fairchild ECL
Contextual Info: ECL ISOPLANAR MEMORY F10410 256xl-BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D E S C R IP T IO N The F 1 041 0 is a 2 5 6 -b it R e a d /W rite Random Access M em ory, organized 256 w ord s by one bit. It has typical access tim e of 18 ns and is

1117 fairchild

Contextual Info: ECL ISOPLANAR MEMORY F10411 256x1—BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D E S C R IP T IO N - The F10411 is a lo w voltage 2 5 6 -b it R e a d /W rite R an­ dom Access M em ory, organized 2 5 6 w ord s by one bit. It has a 2 0 ns typical access tim e

Contextual Info: ECL ISOPLANAR MEMORY F10405 128x l-B IT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE C O M P E N S A T E D ECL G E N E R A L D ESC R IPTIO N - The F10405 is a 128-bit Read/W rite Random Access Mem­ ory, organized 128 w ords by one bit. It has ty p ic a l access tim e o f 12 ns and is designed

si117

Contextual Info: F10136 • F10536 • F10137 • F10537 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10136/F10536 and F10137/F10537 are 4-stage synchronous counters capable of operating at typical count rates ot 250 MHz. The circuits are designed

fairchild ECL

Abstract: F10137 F10136 F10536 F10537 ECL Handbook 125-250MHz
Contextual Info: F10136^ F10536 • F10137 • F10537 V 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL D ESCRIPTIO N - The F10136/F10536 and F10137/F10537 are 4-stage synchronous counters capable o f operating at typical count rates of 250 MHz. The circuits are designed

Contextual Info: F10113 • F10513 ^ QUAD EXCLUSIVE OR WITH ENABLE F10K VOLTAGE COMPENSATED ECL DESCRIPTION — The F10113 and F10513 are Quad Exclusive OR Gates, with an Enable common to all four gates. When the Enable E input is HIGH, all outputs are forced LOW. LOGIC SYMBOL

bcd counter using j-k flip flop diagram

Abstract: pn sequence generator using jk flip flop F10136 ECL Handbook
Contextual Info: / / / F10136 • F10536 • F10137 • F10537 V 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10136/F10536 and F10137/FI 0537 are 4-stage synchronous counters capable of operating at typical count rates of 250 MHz. The circuits are designed

F10165

Abstract: F10565
Contextual Info: F 1 5 6 5 » F 1 1 6 5 ^ 8-INPUT PRIORITY ENCODER F10K VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION - The F10165/F10565 are 8-Input Priority Encoders with output latches. The inputs are preassigned an order of priority, with D0 having the highest priority and

Contextual Info: F10113 • F10513 QUAD EXCLUSIVE OR WITH ENABLE F10K VOLTAGE COMPENSATED ECL DESCRIPTION — The F10113 and F10513 are Quad Exclusive OR Gates, with an Enable common to all four gates. When the Enable E input is HIGH, all outputs are forced LOW. LO G IC SYMBOL

F10145ADC

Abstract: f10145a
Contextual Info: FAIRCHIU3 F10145A 16x4 Register File RAM A Schtumberger Company F10K ECL Product Description The F10145A and F10545A are high-speed 64-bit Random Access Memories organized as a 16-word by 4-bit array. External logic requirements are minimized by internal address decoding, while memory expansion

F10113

Abstract: fairchild ECL
Contextual Info: F10113 • F10513 QUAD EXCLUSIVE OR WITH ENABLE F10K VOLTAGE COMPENSATED ECL DESCRIPTION The F10113 and F10513 are Quad Exclusive OR Gates w ith an Enable common to all fo u r gates. When the Enable E input is HIGH, all outputs are forced LOW. LOGIC SYM BOL