EADB Search Results

74hc793

Abstract: HC793 MC74HCXXXN LS79 74HC79
Contextual Info: MOTOROLA n SE M IC O N D U C T O R 4 8 ^ 7 e? TECHNICAL DATA . MC54/74HC793 r' Product Preview ^ ' J S U F F IX C E R A M IC C A S E 732 O c ta l 3 -S ta te N o n in v e rtin g T ra n s p a re n t L atc h w ith R eadback N S U F F IX P L A S T IC C A S E 738

74hc7793

Abstract: HC7793 MC74HCXXXXN
Contextual Info: MOTOROLA S E M IC O N D U C T O R TECHNICAL DATA MC54/74HC7793 Product Preview iM o n in ve rtin g T ra n s p a re n t L atc h w ith R eadback J S U F F IX C E R A M IC C A S E 732 [I N S U F F IX P L A S T IC C A S E 738 H ig h -P e rfo rm a n c e S ilic o n -G a te C M O S

Contextual Info: S E M IC O N D U C T O R tm 74FR900 9-Bit, 3-Port Latchable Datapath Multiplexer General Description Features The ’FR900 is a d ata bus m ultiplexer routing any of three 9-bit ports to a ny o ther one o f th e three ports. R eadback of data latched from any port onto itself is also possible. The

AD7846

Abstract: AD7846JN AD7846JP AD7846KN AD7846KP HP5082-2811 OTT set top box T-34040
Contextual Info: ► AN ALO G D E V IC E S LC2M0S 16-Bit Voltage Output DAC AD7846 FEATURES 16-B it M o n o to n ic ity over T e m p e ra tu re ± 2 LSBs In te g ral L in ea rity Error M icro p ro cesso r C o m p a tib le w ith R eadback C a p a b ility U n ip o la r or B ipolar O u tp u t

P43AT

Abstract: RT013 diode p4e diode t1.e
Contextual Info: SHARP SM6003/SM6004/SM6005/SM6006 P IN N A M E I/O P O o /EA D o/EA D B o I/O I/O port P O 1/E A D 1/E A D B 1 I/O POü/EAD î /EADB z I/O PO3/EAD3/EADB3 I/O N-CH/ SCHMITT OPEN TRIG. DRAIN D E S C R IP T IO N E A D o : Address O U T E A D B o : A d d re s s / d a ta I/O

g3303

Abstract: EADB
Contextual Info: _Q£}. St r ip H eadb E c o n o m y L ine FEATURES Available In single, dual, and triple row configurations Side stackable, end stackable upon request Notched for easy breaking .G330333SGS33S ! [-• . 4 4 SPECIFIC ATIONS ENVIRONMEITAL \ Temperatur e Ffenge: -55° C to + 1 2 0 ° C

74als666

Abstract: 74ALS667 2561a
Contextual Info: SN 5 4 A LS 6 6 6 , SN 5 4 A LS6 6 7 , SN 7 4 A LS 6 6 6 , S N 7 4 A LS 6 6 7 8 BIT D TYPE T R A N SP A R E N T R EAD-BACK LATCHES W ITH 3-STATE O U TPU TS D 2 8 5 5 , JUNE 1 9 8 4 - • 3-State l/O-Type Read-Back Inputs • Bus-Structured Pinout • Choice of True or Inverting Logic

Contextual Info: Tem ic DG534A/538A S e m i c o n d u c t o r s 4-/8-Channel Wideband Video Multiplexers Features Benefits Applications • • W ide B andw idth: 500 M H z • Im proved S ystem B andw idth • Very Low C rosstalk: - 9 7 dB @ 5 M H z • Im proved C hannel O ff-Isolation

interface 8254 with 8086

Abstract: CA82C54-10 80286 microprocessor pin out diagram 8086 interfacing with 8254 peripheral CA82C54 CA82C54-5 CA82C54-8 MD500 QQQ1213 16CW16
Contextual Info: NElilBRIDGE MICROSYSTEMS SflE ]> • b5ûô] Dl 0DD1210 Obi ■ NBMC CA82C54 PROGRAMMABLE INTERVAL TIMER A high performance device featuring pin and functional compatibility with the industry standard 8254 Supports 8086/88 and 80186/188 micro­ processors

Contextual Info: HXILINX Virtex 2,5 ¥ Field Programmable Gate Arrays N ovem ber 9, 1998 Version 1.1 - AD VAN C E P roduct S pecification Features • • • • • • Fast, high-density Field-P rogram m able Gate Arrays - D ensities from 50 k to 1M system gates - System perform ance up to 200 MHz

Contextual Info: Spartan and SpartanXL Families Field Programmable Gate Arrays £ XILINX January 6 , 1999 Version 1.4 Prelim inary Product Specification Introduction • The S partan Series is the first high-volum e production FPGA solution to deliver all the key requirem ents for ASIC

Contextual Info: £ XILINX Virtex 2.5 V Field Programmable Gate Arrays February 16, 1999 Version 1.3 Advance Product Specification Features • • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz

Contextual Info: V ir te x 2 .5 V £ XILINX Field Programmable Gate Arrays May 13, 1999 Version 1.5 Advance Product Specification Features • • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz

Xilinx XC3090A

Abstract: crystal KDS 4m his 3020a
Contextual Info: XC3000 Series Field Programmable Gate Arrays XC3000A/L, XC31OOA/L O lL IN X Novem ber 9, 1998 (Version 3.1) Product Description Features • • • • • • • • C om plete line of four related Field Program m able Gate A rray product fam ilies

Contextual Info: XC4000, XC4000A, XC4000H Logic Cell Array Families f l XILINX Product Description Features D e sc rip tio n • Third Generation Field-Programmable Gate Arrays - Abundant flip-flops - Flexible function generators - On-chip ultra-fast RAM - Dedicated high-speed carry-propagation circuit

Contextual Info: XILIU001 £ XILINX XC4000 Series Table of Contents XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E and XC4000X Series Features. 3 Low-Voltage Versions A vailable. 3

HARRIS 82C54

Abstract: CS82C54-10 P82C54
Contextual Info: HARRIS SEMICOND SECTOR MbE D • M302E71 DD3flb'fll 3 « H A S R O C ' R A H A R R I S S E M I C O N D U C T O R i / i f a T - 3 Z .- 3 3 - 0 5 February CM OS Programmable Interval Timer 1992 Features Description • 10MHz or 8MHz Clock Input Frequency The Harris 82C54 is a high performance C M O S Programma­

Contextual Info: IBM0316409C IBM0316809C IBM0316169C 16Mb Synchronous DRAM Features • High Performance: fcK Clock Frequency • Multiple Burst Read with Single W rite Option -10 CL-3 -12 CL-3 Units ! • Automatic and Controlled Precharge Command 100 83 MHz ! • Data Mask for Read/Write control x4,x8

68HC11

Abstract: NC11 NC12 XRT83L38 XRT83L38IB B8ZS* encoding
Contextual Info: XRT83L38 OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR JUNE 2007 REV. 1.0.2 GENERAL DESCRIPTION The XRT83L38 is a fully integrated Octal eight channel long-haul and short-haul line interface unit for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or

Contextual Info: £ HARRIS 82C 54/883 june 1989 CMOS Programm able Interval Timer P ino u ts F eatures 8 2 C 5 4 /8 8 3 (CERAMIC DIP) TOP VIEW • This Circuit is Processed in Accordance to M iI-S td -8 8 3 and is Fully Conform ant Under the Provisions of Paragraph 1.2.1.

16121FP

Abstract: 16120fp
Contextual Info: HA161 14 P/ FP, H A 1 6 1 2 0 F P S w i t c h i n g R e gu l a t o r for C h o p p e r Type D C / D C C o n v e r t e r Description Functions The HA 16114P/FP and H A 16120FP are single­ channel PWM switching regulator controller ICs su ita b le fo r c h o p p er-ty p e D C /D C c o n v erters.

Contextual Info: CMOS Programmable Interval Timer Features o « p c i H A R R IS Pinouts • Compatible with NMOS 8254 ► Enhanced Version of NMOS 8253 • 8M Hz Clock Input Frequency • Three Independent 16 Bit Counters • Six Programmable Counter Modes • Status Read Back Command

dmo 265

Abstract: T83L34
Contextual Info: XRT83L34 QUAD T1/E1/J1 LH/SH LIU WITH CLOCK RECOVERY AND JITTER ATTENUATOR SEPTEMBER 2007 REV. 1.0.2 GENERAL DESCRIPTION The XRT83L34 is a fully integrated Quad four channel long-haul and short-haul line interface unit for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or

Nec concurrent rdram

Abstract: concurrent rdram NEC concurrent rdram CI 7424
Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT |xPD488170 18M bit Rambus DRAM 1 Mword x 9bit x 2bank Description |J The 18-Megabit Rambus DRAM (RDRAM™) Is an extremely-high-speed CMOS DRAM organized a sJM w o r llb y 9 bits and capable of bursting up to 256 bytes of data at 2 ns per byte. The use of Rambus S igrgling L o 1 |l% |S L )