EACH Search Results

Fdd spindle motor ncl

Abstract: pll motor control
Contextual Info: TC9203P/F PLL MOTOR CONTROL FOR FDD TC9203P/F are C 2MOS LSI designed for controlling the motor of especially for Disk Spindle Drive FDD . 8-bit D/A converter system has been employed for each of the speed control system (AFC) and the phase control system (APC) and realize a wide reduction of

Toshiba TB 1230 N

Abstract: TMPZ84C011 TMPZ84C011A TMP284C011 FO34
Contextual Info: TOSHIBA TMPZ84C011A 3. OPERATIONAL DESCRIPTIONS 3.1 ENTIRE BLOCK DIAGRAM AND OPERATION OF EACH BLOCK 3.1.1 Entire Block Diagram 110489 Figure 3.1.1 Entire Block Diagram MPUZ80-302 TOSHIBA TMPZ84C011A 3.1.2 Operation of Each Block The TMPZ84C011A largely consists of a processor MPU , a counter/timer circuit

2N3051

Abstract: 2N3050 2N2412 2n3049
Contextual Info: TYPES 2N3049, 2N3050, 2N3051 DUAL P-N-P SILICON TRANSISTORS B U L L E T I N N O . D L -S 6 7 4 2 3 0 , A U G U S T 1 9 6 3 - R E V I S E D A P H IL 1 96 7 DESIGNED FOR DIFFERENTIAL AMPLIFIERS, LOW-NOISE AMPLIFIERS, AND LOW-LEVEL SWITCHING • Each Triode Electrically Similar to 2N2411 and 2N2412 Transistors

Contextual Info: S N 5 4 A LS 2 2 9 A , S N 7 4 A LS 2 2 9 A 1 6 x 5 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES D 2 8 7 6 . M A R C H 1 9 8 6 -R E V IS E D M A Y 1 9 8 6 • Independent Asychronous Inputs and Outputs • 16 Words by 5 Bits Each • Data Rates from 0 to 30 MHz

TA76494

Abstract: TC9192 TA8443 QFP60 TA8444F TA8443F TA8444 pll motor control fg fv sta 515 vh va77
Contextual Info: TA8444F PRELIMINARY DATA DOUBLE PLL-PWM 3-PHASE HALL MOTOR PRE-DRIVER TA844F is 3-phase hall motor pre-driver with PLL controller and PWM controller. 8 bit D/A converter system has been employed for each of the speed control system AFC and the phase control system (APC).

Block DIAGRAM LED TV

Abstract: TA7717AP CIRCUIT DIAGRAM OF COLOR TOSHIBA TV ta7717 TA771 tv led driver circuit diagram DIAGRAM LED TV toshiba tv led Tv Diagram toshiba
Contextual Info: TOSHIBA TA7717AP AUDIO-VIDEO SWITCH FOR A COLOR T V , Unit: The TA7717AP is a system SW IC for a color TV. This system consists of two audio channel switches and a video channel switch controled by two digits TTL level. Each switch has four input terminals and three output

LS 7475

Abstract: C4408
Contextual Info: SN5475, SN5477, SN54LS75, SN54LS77. SN7475, SN74LS75 4 BIT BISTABLE LATCHES MAR CH 1 9 7 4 - each latch (TOP VIEW) OUTPUTS INPUTS REVISED M A R C H 1 9 8 8 SN 5475 , SN 54LS75 . . . J OR W PACKAGE S N 7475 . . . N PACKAGE SN 74LS 75 . . . D O R N PACKAGE

Contextual Info: SN55563A, SN55564A ELECTROLUMINESCENT ROW DRIVERS D 3 3 1 3 , OCTOBER 1 9 8 9 S N 55S63A . . . FJ PACKAGE • Each Device Drives 34 Electrodes • Selectable Open-Source or Open-Drain Output • Outputs Rated at 225 V • Output Current Capability: - 9 0 mA to 150 mA

Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4530BP TC4530BP DUAL 5-INPUT MAJORITY LOGIC GATE The TC45 30BP is dual 5-input majority logic gate. Each majority logic gate decides whether or not the input at "H" level is more than that at "L" level.

"MARKING TE" US6

Abstract: 2301 mini transistor
Contextual Info: [3 ] Application Information 1. Overview 2. Device Marking [ 3 ] Application Information 1. Overview Toshiba B ias Resistor Transistors BR T s each contain a built-in base series resistor and baseem itter bias resistor. This helps you reduce the parts count in circuits to m iniaturize equipment

74als2238

Contextual Info: SN74ALS2238 32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY D3501, A P R IL 1990 N PACKAQE TOP VIEW Independent Asychronous Input« and Outputs Bidirectional RSTK 32 Word« by 9 BK. Each * Data Rate« from 0 to 40 MHz * F a ll-T h ro u g h T im e . . . 2 2 n « iy p

Applications Note U-137

Contextual Info: y UNITRODE UCC1776 UCC2776 UCC3776 PRELIMINARY Quad FET Driver FEATURES DESCRIPTION • High Peak Output Current Each Output - 1.5A Source, 2.0A Sink • W ide Operating Voltage Range 4.5V to 18V • Thermal Shutdown • CMOS Compatible Inputs • Outputs Are Active Low

3D16A-P

Abstract: F14GB-P F14G 3D16A 6D28A-P
Contextual Info: D I P - 8 P I N O U T L I N E DRAWING 3D8A-P U n it i n mm i~i r~I I—I + 0.1 0-Ä5-0.0 5 Note) Lead pitch is 2.54 and tolerance is ±0.25 against theoretical center of each lead that is obtained on the b asis of N o . l and N o . 14 leads. 651 DI P 16 P I N O U T L I N E DRAWING

ttl 74100

Abstract: 74100 74100 Latch IC TTL 74100 54100
Contextual Info: TYPES SN54W0, SN74100 8-BIT BISTASIE UTCHES ttl MSI B U L L E T IN N O . D L - S 7211830, D E C E M B E R 1972 " S J 5 Ï Ï » . . . J OR W PACKAGE SNS4100 . . . i OB N PACKAGE TOP VIEW logic FUNCTION TABLE (Each Latch) INPUTS G L H H H X L •^ . .

Contextual Info: TL16C552 DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO _ SLLS102B - DECEMBER 1990 - REVISED MARCH 1996 • IBM PC/AT Compatible • Programmable Serial Interface Characteristics for Each Channel: - 5-, 6-, 7-, or 8-bit Characters

Contextual Info: SN54HC393, SN74HC393 DUAL 4-BIT BINARY COUNTERS SCLS143B – DECEMBER 1982 – REVISED MAY 1997 D D D D Dual 4-Bit Binary Counters With Individual Clocks Direct Clear for Each 4-Bit Counter Can Significantly Improve System Densities by Reducing Counter Package

TUG-3

Abstract: vc-4 digital cross connect
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453B TECHNICAL OVERVIEW Each of the three channels of the TL3M can map a DS3 line signal into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET signal. An E3 signal can be mapped only into an STM-1 TUG-3. The TL3M interfaces to an STM-1 or STS-3 SDH/SONET signal

reset IC sot23

Contextual Info: XC61F Series ETR0202_004a Voltage Detectors, Delay Circuit Built-In •GENERAL DESCRIPTION The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. A delay circuit is built-in to each detector.

Contextual Info: SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B – DECEMBER 1982 – REVISED MAY 1997 D D D D Contain Eight Flip-Flops With Single-Rail Outputs Direct Clear Input Individual Data Input to Each Flip-Flop Applications Include: – Buffer/Storage Registers

Contextual Info: Envoy -8FE Device Octal Fast Ethernet Controller TXC-06840 FEATURES DESCRIPTION • 8 Independent SMII ports operating at 10/100 Mbit/s mixed mode • 8 Media Access Controllers MACs each connected to an SMII port • POS-PHY Level 2 interface operating at 50 MHz

of TX6A RX6A

Abstract: RX6A tx2c transmitter RX6a 1211 TX1B TXC-06885 diode GFP AA tx6c TX5b rx5b Ethernet over SONET mapper
Contextual Info: Envoy -CE4 Device SPI-3 to Ethernet Controller TXC-06885 DATA SHEET PRODUCT PREVIEW • 4 Configurable Media Access Controllers MACs • Each MAC is configurable as 8 Fast Ethernet ports (10/100 Mbits/s) or 2 Fast Ethernet ports with extended buffers or 1 Gigabit Ethernet port (10/100/1000 Mbits/s)

PR 302

Abstract: D3601-1 A384
Contextual Info: Pomona Model 3601 Die Cast Aluminum Box Painted, Size “D” MATERIALS: Screws: 4 each #4-40 x 6.35 1/4” Phillips pan head pr MS 35206-213 with blue zinc plating. Cover: 1.60 (.063) thick aluminum Alloy 1100-H14 Finish: Clear anodized per MIL-A-8625,

NL10276BC16-01

Abstract: NL10276BC 84PW0
Contextual Info: Product Number: NL10276BC16-01 8.4 inches XGA for Industrial applications UA-SFT Screen size 8.4 inch 21cm diagonal Interface LVDS (RGB 8bits each / 6 bits each) Resolution 1024(H) x 768(V) pixels Power supply voltage 3.3V Display area 170.496(H) x 127.872(V) mm

MC14517

Abstract: 14517B Q32B Q32A
Contextual Info: MC14517B Dual 64-Bit Static Shift Register The MC14517B dual 64−bit static shift register consists of two identical, independent, 64−bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data