E1 FRAM Search Results

signalling and frame alignment in E1

Contextual Info: PMC-Sierra,Inc. PM6388 EOCTL Preliminary Octal E1 Framer FEATURES • Monolithic single-chip device that integrates eight datacom E1 framers and transmitters for terminating duplex E1 signals. • Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1

PB-0016-1199-5K

Abstract: LXT386 LEVEL ONE COMMUNICATIONS LXT380 level one microwave transceiver microwave transceiver specification G-772 E1 HDB3
Contextual Info: QUAD T1/E1/J1 TRANSCEIVER Product Brief LXT386 QUAD T1/E1/J1 TRANSCEIVER Remote Access Wireless Infrastructure T1/E1 T1/E1 DSU/CSU Router Access Switch Add-Drop MUX SONET/SDH Ring T1/E1 Interface Internet Access POTS Service T1/E1 Add-Drop MUX Remote Access

Contextual Info: Preliminary Data Sheet May 1997 microelectronics group Lucent Technologies Bell Labs Innovations T7698 QuadT1/E1 Line Interface and Octal T1/E1 Monitor Features • Fully integrated quad T1/E1 line transceiver and octal T1/E1 receive framer/monitor with HDLC pro­

ITU-T G964

Abstract: PM6344 PM6388 PM7366 PM4314 PM4351 PM4388 PM6341 signalling and frame alignment in E1 "TOPS"
Contextual Info: PMC-Sierra,Inc. PM6388 EOCTL Preliminary Octal E1 Framer FEATURES • Monolithic single-chip device that integrates eight datacom E1 framers and transmitters for terminating duplex E1 signals. • Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1

Contextual Info: Data Sheet January 1999 microelectronics group Lucent Technologies Bell Labs Innovations T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features • Integrated quad T1/E1 line interface and octal T1/ E1 receive frame monitor with HDLC processor provides system QoS capabilities.

Contextual Info: Preliminary Data Sheet May 1998 microel ect ro nic s group Lucent Technologies Bell Labs Innovations T7698 QuadT1/E1 Line Interface and Octal T1/E1 Monitor Features • Fully integrated quadT1/E1 line interface and octal T1/E1 receive framer/monitor with HDLC proces­

8051 Read Write for 80c188

Abstract: 68HC11 80C188 I960 TS16 XRT84V24 XRT84V24IV-208 E1 frame FSRC
Contextual Info: áç XRT84V24 PRELIMINARY QUAD E1 FRAMER IC JUNE 2001 REV. P1.0.4 GENERAL DESCRIPTION • Contains two 96 byte Transmit HDLC Buffers and two 96 byte Receive HDLC buffers for each channel The XRT84V24 Quad E1 Framer contains four independent E1 Framer blocks. Each E1 Framer block

DS21Q354

Abstract: DS21Q42 DS21Q44 DS2141 DS2143 DS2151 DS21FF42 DS21FF44 DS21FT42 DS21FT44
Contextual Info: Maxim > App Notes > TELECOM Keywords: T1, E1, T1/E1, single chip transceivers, SCT, framer, fractional, looped-timed, channel, port May 04, 2001 APPLICATION NOTE 309 Interfacing to the Fractional T1 and E1 Abstract: This application note provides an example fractional T1 and E1 circuit design using Dallas

CHN G4 136

Abstract: chn7 SA8 357 TR54016 XRT83L38 XRT84L38 XRT84L38IB 7174B 8ch LOW SATURATION DRIVER C1-168
Contextual Info: XRT84L38 OCTAL T1/E1/J1 FRAMER SEPTEMBER 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error

Lucent SLC 2000

Abstract: f 4556 GR-253-CORE GR-499-CORE T7690 T7698 SA6H T7698-FL3-DB
Contextual Info: Data Sheet January 1999 T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features • ■ ■ ■ ■ Integrated quad T1/E1 line interface and octal T1/ E1 receive frame monitor with HDLC processor provides system QoS capabilities. Hardware and software reset options.

ITU-T G964

Abstract: m6388 PM6341 PM6344 PM6388 PM4314 PM4351 PM4388
Contextual Info: PM6388 EOCTL Preliminary Information OCTAL E1 FRAMER FEATURES • Monolithic single chip device which integrates 8 datacom E1 framers and transmitters for terminating duplex E1 signals. • Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals and is consistent with ITU-T

f 4556

Abstract: GR-253-CORE GR-499-CORE T7690 T7698 SR52 W 18
Contextual Info: Data Sheet September 2002 T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features • Integrated quad T1/E1 line interface and octal T1/ E1 receive frame monitor with HDLC processor provides system QoS capabilities. ■ ■ ■ ■ Hardware and software reset options.

GR-253-CORE

Abstract: GR-499-CORE T7630 T7690 T7698 E1 frame
Contextual Info: Product Brief March 1999 T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features • ■ ■ ■ ■ Integrated quad T1/E1 line interface and octal T1/ E1 receive frame monitor with HDLC processor provides system QoS capabilities. Hardware and software reset options.

Contextual Info: STANDARD PRODUCT PMC-951013 1 PM PMC-Sierra, Inc. ISSUE 5 PM6344 EQUAD QUADRUPLE E1 FRAMER FEATURES • Integrates four full-featured E1 fram ers and transm itters in a single device for term inating duplex E1 signals. • Software and functionally com patible with the PM6341 E1XC Single E1

AN034

Abstract: AN204 CS61880 CS61880-IB CS61880-IQ
Contextual Info: CS61880 Octal E1 Line Interface Unit Features Description „ Octal E1 Short-haul Line Interface Unit The CS61880 is a full-featured Octal E1 short-haul LIU that supports 2.048 Mbps data transmission for both E1 75 Ω and E1 120 Ω applications. Each channel provides

1501 0647

Abstract: RELAY 4088 ETS300 JT-G704 PB38 CN8380
Contextual Info: network access products CN8394/8395/8398 Quad/x16/Octal T1/E1/J1 Framers Fully Featured T1/E1/J1 Framers Conexant’s highly integrated T1/E1/J1 framers drive down per-port framer costs, support a scalable system roadmap, and provide a single 3.3 V chip for T1, E1 and J1 applications. They support

Contextual Info: IXF6151 28 T1/E1 Mapper Datasheet The IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/ or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface.

nrz to hdb3

Abstract: LXT6282 E1 HDB3 249279 HDB3 to nrz intel datasheets for i9 microwave radio transmitter surface mount counter G704 LXT334
Contextual Info: LXT6282 Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/Wander Suppression Datasheet LXT6282 is an eight-channel E1 digital interface. It integrates an E1 dejitter phase locked loop, an E1 retiming function and a CRC-4 monitor function for each E1 transmitter and a CRC-4

tms 1951 nl

Contextual Info: Intel IXF3208 Octal T1/E1/J1 Framer with Intel® On-Chip PRM Datasheet Product Features • ■ ■ ■ ■ ■ ■ ■ ■ Octal T1/E1/J1 Framer Software selectable and fully independent T1/E1/J1 operation Support for T1/E1/J1 standards: — T1: T1-SF, T1-ESF, Lucent* SLC®96

DTC24

Abstract: AU-AIS MTC27 vc-4 digital cross connect 226 35K 2x4 TTL demultiplexer Digital Alarm Clock by ttl Digital Alarm Clock by using ttl P03H GR-253-CORE
Contextual Info: IXF6151 28 T1/E1 Mapper Datasheet The IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/ or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface.

CHN G4 124

Abstract: CHN G4 329
Contextual Info: áç XRT84L38 PRELIMINARY OCTAL T1/E1/J1 FRAMER JULY 2003 REV. P1.0.4 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications.

Digital Alarm Clock using 8051

Abstract: chn 448 chn 706 CHN 632 CHN 703 RAM 2112 256 word 32.768mhz pin hole thru chn 608 microcontroller 8051 application of alarm clock octal tri state buffer ic
Contextual Info: áç XRT84L38 OCTAL T1/E1/J1 FRAMER FEBRUARY 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications.

Contextual Info: Intel IXF3208 Octal T1/E1/J1 Framer with Intel® On-Chip PRM Preliminary Datasheet Product Features • ■ ■ ■ ■ ■ ■ ■ ■ Octal T1/E1/J1 Framer Software selectable and fully independent T1/E1/J1 operation Support for T1/E1/J1 standards: — T1: T1-SF, T1-ESF, Lucent* SLC®96

2x4 TTL demultiplexer

Contextual Info: Intel IXF6151 28 T1/E1 Mapper Datasheet The Intel® IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus