DUAL CLOCK FIFO Search Results

DL010

Contextual Info: Dual Direct Rambus Clock Generator ® RAMBUS Overview The Dual Direct Rambus® Clock Generator DRCG-D provides the necessary clock signals to support a Dual channel Direct Rambus memory subsystem. The DRCG-D is a functional extension of the DRCG and maintains memory channel signal integrity. It includes

S2002

Abstract: S2202 7.2 channel receiver
Contextual Info: DEVICE SPECIFICATION DUAL GIGABIT ETHERNET DEVICE DUAL GIGABIT ETHERNET DEVICE FEATURES GENERAL DESCRIPTION • 1250 MHz Gigabit Ethernet operating rate - Half rate operation • Dual Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference

Contextual Info: ADS5404 www.ti.com SLAS945 – APRIL 2013 Dual Channel 12-Bit 500Msps Analog-to-Digital Converter Check for Samples: ADS5404 FEATURES 1 • • • • • • • • • • • Dual Channel 12-Bit Resolution Maximum Clock Rate: 500 Msps Low Swing Fullscale Input: 1.0 Vpp

Contextual Info: TL16C552A DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996 IBM PC/AT Compatible TVk>TL16C550 ACEs Enhanced Bidirectional Printer Port 16-Byte FIFOs Reduce CPU Interrupts Up to 16-MHz Clock Rate for up to 1-Mbaud

Contextual Info: TL16C752C DUAL UART WITH 64-BYTE FIFO www.ti.com SLLS646 – MARCH 2008 FEATURES 1 • • • • • • • • • • • • • ST16C654/654D Pin Compatible With Additional Enhancements PFB Package Only Supports up to 24-MHz Crystal Input Clock (1.5 Mbps)

Contextual Info: TL16C752C DUAL UART WITH 64-BYTE FIFO www.ti.com SLLS646 – MARCH 2008 FEATURES 1 • • • • • • • • • • • • • ST16C654/654D Pin Compatible With Additional Enhancements PFB Package Only Supports up to 24-MHz Crystal Input Clock (1.5 Mbps)

common mode rejection ratio test 1553B

Contextual Info: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor November 2005 GENERAL DESCRIPTION FEATURES ! ! ! ! ! ! ! Monolithic CMOS technology 3.3V operation Exceptionally low power On-chip message buffering Selectable master clock frequency Dual differential 1553 bus transceivers

MIL-STD-1553

Contextual Info: HI-6110 MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor August 2005 GENERAL DESCRIPTION FEATURES ! ! ! ! ! ! ! Monolithic CMOS technology 3.3V operation Exceptionally low power On-chip message buffering Selectable master clock frequency Dual differential 1553 bus transceivers

applications of microprocessor in printer

Abstract: 74LS245 TL16C450 TL16C452 TL16C550 TL16C550B
Contextual Info: TL16C552AI DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189A – NOVEMBER 1994 – REVISED MARCH 1996 D D D D D D D D IBM PC/AT  Compatible Two TL16C550 ACEs Enhanced Bidirectional Printer Port 16-Byte FIFOs Reduce CPU Interrupts Up to 16-MHz Clock Rate for up to 1-Mbaud

Contextual Info: TL16C752 3.3-V DUAL UART WITH 64-BYTE FIFO S L L S 3 0 5 - MAY 1999 • ■ • Pin Compatible With ST16C2550 With Additional Enhancements ■ I V • Supports Up to 3.125 Mbps Baud Rate - Up to 2.1875 Mbps Baud Rate When Using Crystal 35 MHz Input Clock

telcordia gr 1081 core

Abstract: 16 bit processor schematic
Contextual Info: PHAST-6N Device Dual STM-1/OC-3 SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06306B DATA SHEET PRELIMINARY TXC-06306B-MB, Ed. 2 June 2005 FEATURES APPLICATIONS • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery

max3109

Abstract: MAX14830 application notes MAX3109ETJ
Contextual Info: 19-5806; Rev 1; 5/12 Dual Serial UART with 128-Word FIFOs Features S 24Mbps max Baud Rate S Integrated PLL and Divider S 1.71V to 3.6V Supply Range S High-Resolution Programmable Baud Rate S SPI Up to 26MHz Clock Rate S Fast Mode Plus I2C Up to 1MHz S Automatic RTS_ and CTS_ Flow Control

Intel 82750

Contextual Info: inU 82750PB PIXEL PROCESSOR • 25 MHz Clock with Single Cycle Execution ■ Zero Branch Delay ■ Wide Instruction Word Processor ■ 512 x 48-Bit Instruction RAM ■ 512 x 16-Bit Data RAM ■ Two Internal 16-Bit Buses ■ ALU with Dual-Add-Wlth-Saturation

DDC Panel

Abstract: CYBER9320 Trident vga ibm crt monitor circuit diagram Non VGA Video Controller IC flat crt circuit diagram PQ-32/plasma 640x480
Contextual Info: / Trident CYBER9320 Flat Panel Controller Features Highly Integrated Design • Requires only one 256Kxl6 DRAM for 1024x768-16 color SVGA solution • Built-in LUT-DAC composed of 256x18 color look-up table • Dual loop memory and video clock • Two-chip solution 9320 and 256Kxl6 for 512K

CYBER9320

Abstract: PC microsoft keyboard pcb CIRCUIT diagram trident plasma 640x480 800x600-256 trident vga vesa local bus trident 9320 ibm crt monitor circuit diagram crt monitor PCB LAYOUT
Contextual Info: / Trident CYBER932CT Flat Panel Controller Features Highly Integrated Design • Requires only one 256Kxl6 DRAM for 1024x768-16 color SVGA solution • Built-in LUT-DAC composed of 256x18 color look-up table • Dual loop memory and video clock • Two-chip solution 9320 and 256Kxl6 for 5 12K

AD9880 hdcp

Abstract: HDMI TO VGA MONITOR PINOUT AD9880 dvi-i to hdmi pinout AN-775 IEC90658 circuit diagram for sony tv 4 kv HDMI to vga pinout AD9880KSTZ-100 AD9880KSTZ-150
Contextual Info: Analog/HDMI Dual Display Interface AD9880 FEATURES FUNCTIONAL BLOCK DIAGRAM ANALOG INTERFACE R/G/B OR YPbPrIN1 2:1 MUX HSYNC 0 HSYNC 1 HSYNC 0 HSYNC 1 2:1 MUX SOGIN 0 SOGIN 1 2:1 MUX COAST FILT CKINV CKEXT 2:1 MUX R/G/B 8X3 A/D CLAMP SYNC PROCESSING AND CLOCK

Hex schmitt trigger ecl

Abstract: Dual Retriggerable Resettable One Shots ECL 100315 cmos function generator DIP 4 Crystals Clock Generators MM74C14 DIP CRYSTAL MM74C221 monostable ttl
Contextual Info: Logic Products by Function Other Products Logic Product Family Product Description Package Voltage Node 9403A FAST First-In First-Out FIFO Buffer Memory DIP - DM9602 Bipolar-TTL Dual Retriggerable Resettable One Shots DIP 5 DM96L02 Bipolar-TTL Dual Retriggerable Resettable Monostable Multivibrator

IDT72201

Abstract: IDT72211 IDT72221 IDT72231 IDT72801 IDT72811 IDT72821 IDT72831 IDT72841 IDT72851
Contextual Info: Integrated Device Technology, Inc. DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9 FEATURES: • • • • • • • The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs

IC 4093 pin configuration

Abstract: pin diagram ic 4093 Tri-State Buffer CMOS ci 4093 72V841
Contextual Info: 3.3 VOLT DUAL CMOS SyncFlFO DUAL 256 x 9, DUAL 512 x 9, PRELIMINARY IDT72V801 DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9 ¡DT72V821 IDT72V831 ìitegiatsd Devie Technology, lie. IDT72V841 FEATURES: • The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs

72V841

Contextual Info: PRELIMINARY 3.3 VOLT DUAL CMOS SyncFlFO DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9 IDT72V801 IDT72V811 IDT72V821 IDT72V831 IDT72V841 Ii t e g i a t e d D e v ic e T e c h n o i> g y , l i e . FEATURES: • The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs

Contextual Info: 3.3 VOLT DUAL CMOS SyncFlFO DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9 Integrated D ev ice TechnoJogy, S c . FEATURES: • The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs • The IDT72V811 is equivalent to two IDT72V211 5 1 2 x 9 FIFOs

Contextual Info: Integrated Device Technology, Inc. DUAL DUAL DUAL DUAL CMOS SyncFlFO 256 x 9, DUAL 512 x 9, 1,024 x 9, DUAL 2,048 x 9, 4,096 x 9, DUAL 8,192 x 9 FEATURES: • • • • • • • • • • • • • • • The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs

xilinx fifo generator 6.2

Abstract: synchronous fifo xilinx fifo generator timing xilinx fifo fifo generator xilinx spartan
Contextual Info: dsp_fifo.fm Page 135 Tuesday, July 14, 1998 8:07 AM Synchronous FIFO July 17, 1998 Product Specification FIFO UP/DOWN COUNTER R RESET BUFCTR_CE RESET CE Q Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com

62d18

Abstract: fifo ttl B129 B249 SN74ACT2226 SN74ACT2228
Contextual Info: SN74ACT2226, SN74ACT2228 DUAL 6 4 x 1 AND DUAL 256x1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219A - JUNE 1992-R E V IS E D AUGUST 1993 Dual Independent FIFOs Organized as: - 64 Words by 1 Bit Each - SN74ACT2226 - 256 Words by 1 Bit Each - SN74ACT2228 Free-Running Read and Write Clocks Can