DUAL 80 BIT STATIC SHIFT REGISTER Search Results

lr 3103

Abstract: D012 PW02 TMS3102LC TMS3103LC
Contextual Info: TMS 3101 LC, N C -DUAL 100-BIT STATIC SHIFT REGISTER TMS 3102 LC, N C -DUAL 80-BIT STATIC SHIFT REGISTER TMS 3103 LC, NC-DUAL 64-BIT STATIC SHIFT REGISTER MOS LSI features DC to 2.5-MHz operation Low power dissipation Direct interface with DTL/TTL Static operation

shift register ttl

Abstract: A 3101 8 pin td 3101 n D021 PW02 SN74I
Contextual Info: T M S 3101 LC, N C -DUAL 100-BIT STATIC SHIFT REGISTER T M S 3102 LC, N C -DUAL 80-BIT STATIC SHIFT REGISTER T M S 3103 LC, N C -DUAL 64-BIT STATIC SHIFT REGISTER features • > z DC to 2.5-M H z operation • Low power dissipation § 3 „•< • D irect interface w ith D T L /T T L

MM5053

Abstract: MM4053H MM5052 MM5053H dual 80 bit static shift register MM4052 MM-505
Contextual Info: M M4052/MM5052, M M 4053/M M 5053 jgg National ÆjA Semiconductor Shift Registers M M 4052/M M 5052 Dual 80-Bit Static Shift Register M M 4053/M M 5053 Dual 100-Blt Static Shift Register general description The M M 4 0 5 2 /M M 5 0 5 2 dual 8 0 -b it and M M 4 0 5 3 /

HEF SCHMITT-TRIGGER IN

Abstract: HE4000B HEF4517B HEF4517BD HEF4517BP HEF4517BT O32B O64A
Contextual Info: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4517B LSI Dual 64-bit static shift register

4-DIGIT counter with 7-SEGMENT DISPLAY

Abstract: binary to hex led display decoder TC5000 tc5067 IC451 IC-451 tc4036 TC5066 TC4012 Multivibrator 555
Contextual Info: TC4000 Series PAGE FUNCTION PRODUCT NAME TC4000BP DUAL 3 INPUT NOR GATE PLUS INVERTER 75 TC4001BP/BF/BFN QUAD 2 INPUT N OR GATE 80 TC4001UBP QUAD 2 INPUT NOR GATE 83 TC4002BP/BF DUAL 4 INPUT NOR GATE 80 18-STAGE STATIC SHIFT REGISTER V ' ' 86 1/ "TC4006BP

TC4072BP

Abstract: 4 bit binary divider HIGH SPEED FREQUENCY DIVIDER TC5032P TC4584 7-stage frequency divider TC5000 tc4036 TC5001 TC4029BP
Contextual Info: TC4000 Series PRODUCT NAME FUNCTION PAGE TC4000BP DUAL 3 INPUT NOR GATE PLUS INVERTER 75 TC4001BP/BF QUAD 2 INPUT NOR GATE 80 TC4001UBP QUAD 2 INPUT NOR GATE 83 TC4002BP/BF DUAL 4 INPUT NOR GATE 80 TC4006BP 18-STAGE STATIC SHIFT REGISTER 86 TC4007UBP/UBF DUAL COMPLEMENTARY PAIR+INVERTER

TC350I

Abstract: binary to hex led display decoder Hex to 7 Segment converter 4-DIGIT counter with 7-SEGMENT DISPLAY tc5000 TC4516 TC35072 TC5032P TC4039 4 digit LCD bcd COUNTER
Contextual Info: TC4000 Series FUNCTION PRODUCT NAME PAGE DUAL 3 INPUT NOR GATE PLUS INVERTER 75 TC4001BP/BF/BFN QUAD 2 INPUT NOR GATE 80 TC4001UBP QUAD 2 INPUT NOR GATE 83 TC4002BP/BF DUAL 4 INPUT NOR GATE 80 TC4006BP 18-STAGE STATIC SHIFT REGISTER 86 TC4007UBP/UBF DUAL COMPLEMENTARY PAIR+INVERTER

HE4000B

Abstract: HEF4517B HEF4517BD HEF4517BP HEF4517BT O64A
Contextual Info: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4517B LSI Dual 64-bit static shift register

Contextual Info: HEF4517B LSI DUAL 64-BIT STATIC SHIFT REGISTER The HEF4517B consists o f two identical, independent 64-bit static shift registers. Each register has separate clock CP , data input (O), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th b it positions (O ig to 0 $4). Data at the D input is entered

HEF4517B

Abstract: HEF4517BD HEF4517BP
Contextual Info: HEF4517B LSI DUAL 64-BIT STATIC SHIFT REGISTER The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock CP , data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions <Oi0 to Og4 ). Data at the D input is entered

HEF4517B

Abstract: HEF4517BP HEF4517BT
Contextual Info: HEF4517B Dual 64-bit static shift register Rev. 05 — 28 July 2009 Product data sheet 1. General description The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock nCP , data input (nD), parallel input-enable/output-enable

HEF4517B

Abstract: HEF4517BP HEF4517BT JESD22-A114E
Contextual Info: HEF4517B Dual 64-bit static shift register Rev. 04 — 6 April 2009 Product data sheet 1. General description The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock nCP , data input (nD), parallel input-enable/output-enable

HEF4517B

Abstract: HEF4517BP HEF4517BT
Contextual Info: HEF4517B Dual 64-bit static shift register Rev. 06 — 10 December 2009 Product data sheet 1. General description The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock nCP , data input (nD), parallel input-enable/output-enable

Contextual Info: HEF4517B Dual 64-bit static shift register Rev. 7 — 11 November 2011 Product data sheet 1. General description The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock nCP , data input (nD), parallel input-enable/output-enable

Contextual Info: Reduction in Power Dissipation of Mos Static Shift Registers by Pulsing Device Supply Rails A pplication Report B97 ar\ Texas Instruments Limited • Manton Lane • Bedford • Phone 0234 67466 • Telex 82178 SUM M ARY This report shows that a reduction in power dissipation of each register to approximately 1/500 of the

MC14517B

Abstract: Q32B 14517B
Contextual Info: MC14517B Dual 64-Bit Static Shift Register The MC14517B dual 64–bit static shift register consists of two identical, independent, 64–bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data

tms 374

Abstract: tms 374 chip 3126 "pin compatible" 136 8PIN
Contextual Info: MOS LSI TMS 3126, 3127, 31-28, 3129, 3130, 3131, 3132 LC, NC DUAL 96-, 100-, 128-, 132-, 133-, 136-, 144-81T STATIC SHIFT REGISTERS BULLETIN NO. DL•S 7512263, MAY 1975 • DC to 2.5-MHz Operation • Static Configuration • Single TTL-Compatible Clock TO·99 HERMETICALLY SEALED PACKAGE

Q32B

Abstract: Q32A 4000B 4517B SCL4517B
Contextual Info: 4517B INTERNATIONAL, INC. CMOS 64-BIT DUAL SHIFT REGISTER FEATURES • Independent Clock, Write Enable Inputs • Static Operation • Positive Edge-Clocked Design • 6.7MHz Toggle Rate @ 10 VDC • Tri-State Output at 64th Bit • Balanced Output Drive Current Specifications

Contextual Info: R&E 4517B INTERNATIONAL, INC CMOS 64-BIT DUAL SHIFT REGISTER FEATURES • Independent Clock, W rite Enable Inputs • Static Operation • Positive Edge-Clocked Design • 6.7MHz Toggle Rate @ 10 VD C • Tri-State Output at 64th Bit • Balanced Output Drive Current Specifications

V7000

Contextual Info: HEF4517B LSI J DUAL 64-BIT STATIC SHIFT REGISTER The HEF4517B consists o f tw o identical, independent 64-bit static shift registers. Each register has separate clock CP , data in pu t ( D), parallel input-enable/output-enable (PE/EO) and fo u r 3-state outputs o f the 16th, 32nd, 48th and 64th b it positions (0 -|6 to O5 4 ). Data at the D in pu t is entered

mc14569

Abstract: mc14094b MC14024B MC14555B
Contextual Info: CMOS Selection Guide by Function Device NAND Gates MC14011B MC14011UB MC14093B MC14023B Function Page Quad 2−Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Quad 2−Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

mc1413 darlington pair

Abstract: MC1413 mc14094b MC14569 MC14024B MC14555B
Contextual Info: Table of Contents Page Page Numeric Data Sheet Listing Chapter 2: Data Sheets Numeric Data Sheet Listing . . . . . . . . . . . . . . . . . . . . . . . . . 4 Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 1: Selector Guide

Q32B

Abstract: 14517B 14517B/BEAJC
Contextual Info: MC14517B Dual 64−Bit Static Shift Register The MC14517B dual 64−bit static shift register consists of two identical, independent, 64−bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data

FZK101

Abstract: FZK105 upd101 SNF10 SN76131 TAA700 FZH111 FZJ101 MFC8010 MFC8001
Contextual Info: HANDBOOK OF INTESBATEI CIRCUITS in EQUIVALENTS AND SUBSTITUTES A lthough every care is taken with the preparation of this book, the publishers will not be responsible for any errors that might occur. I.S.B.N. 0 900162 35 X 1974 by Bernard B. Babani First Published 1974