DTC20 Search Results

7408, 7404, 7486, 7432

Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
Contextual Info: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers

R11220K

Contextual Info: 2002.08.27 2CH PWM DC/DC Controller R1280D002X Series n OUTLINE The R1280D002X Series are 2-channel PWM Step-up as Channel 1 /Inverting (as Channel 2) DC/DC converter controllers with CMOS process. Each of the R1280D002X Series consists of an oscillator, a PWM control circuit, a reference voltage unit, an

Contextual Info: P ro d u c t O vervie FEBRUARY 1998 Revision 1.0 SXT6251 21E1 Mapper General Description The SXT6251 21E1 Mapper performs asynchronous map­ ping and demapping of 21 E l PDH signals into SDH. The PDH side interfaces with E l LIU and framers via NRZ Clock & Data, while the SDH side uses a standard Telecom

434 289

Abstract: 54175 S085 54151 gen 24lJ IPI04LJ NA220 DTB20
Contextual Info: TGC100M MILITARY SERIES 1-/im CMOS GATE ARRAYS Release 2.0, A PR IL 1989 * AC PERFORMANCE TEST STRUCTURE Fully Characterized for M ilitary Applications — Product Fully Compliant w ith the Requirements of M IL -S T D -883 Paragraph 1.2.1 Is Available — Production Processing Is in Accordance

dtc12

Contextual Info: DATA SHEET JUNE 1999 Revision 2.0 LXT6251 21 E1 SDH Mapper General Description Features The LXT6251 21E1 Mapper performs asynchronous mapping and demapping of 21 E l PDH signals into SDH. The PDH side interfaces with E l LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard

Contextual Info: IXF6151 28 T1/E1 Mapper Datasheet The IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/ or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface.

MTC27

Abstract: 2x4 TTL demultiplexer 106 35K 045 226 35K AU-AIS Digital Alarm Clock by using ttl MTB 230 P03H GR-253-CORE IXF6151
Contextual Info: IXF6151 28 T1/E1 Mapper Datasheet The IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/ or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface.

Contextual Info: Platform.book Page 1 Thursday, March 21, 2013 4:14 PM CodeWarrior Development Studio for Power Architecture Processors Version 10.x Targeting Manual Revised: 21 March 2013 Platform.book Page 2 Thursday, March 21, 2013 4:14 PM Freescale, the Freescale logo, CodeWarrior, PowerQUICC, QorIQ, Qorivva, StarCore are trademarks of Freescale

san francisco telecom

Abstract: X1HB 001H MTC21 SXT6251 MTC11 MTD16 P1396 MTC13 MTC15
Contextual Info: DATA SHEET MAY 1998 Revision 1.1 SXT6251 21 E1 SDH Mapper General Description Features The SXT6251 21E1 Mapper performs asynchronous mapping and demapping of 21 E1 PDH signals into SDH. The PDH side interfaces with E1 LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard Telecom

Contextual Info: Product Folder Sample & Buy Technical Documents Tools & Software Support & Community UCD8220-Q1 SLUSB36B – JUNE 2012 – REVISED JULY 2014 UCD8220-Q1 Digitally Managed Push-Pull Analog PWM Controllers 1 Features • 1 • • • • • • • • •

LXT6282

Abstract: DTD17 MTC11 MTC15 header 3x2 LXT6251A intel C96 74HC04 LXT344 25X2
Contextual Info: POWER.SCH POWER SUPPLIES MHICLK MHICLK J3 EXTCLKA EXTCLKA MHBCLK MHBCLK BNC-4 LXT6051.SCH J4 EXTCLKB MRESET EXTCLKB ALTSOH.sch BNC-4 MRESET MRESET J5 EXTCLKC MRESET EXTCLKC TSYNCCLKM TSYNCCLKM BNC-4 FPGA FOR SERIAL ACCESS TSYNCCLKM LXT6051A ORDERWIR.SCH TROWM

transistor c103m

Abstract: C103M c105m W41l c105m TRANSISTOR c103m TRANSISTOR C103M equivalent 54175 4013 bt CMOS Sc 54155
Contextual Info: TGC100M MILITARY SERIES 1/im CMOS GATE ARRAYS Release 2.0, APRIL 1989 Fully Characterized for Military Applications — Product Fully Compliant with the Requirements of M IL-STD-883 Paragraph 1.2.1 Is Available — Production Processing Is in Accordance with the General Requirements of

MTC27

Abstract: 2x4 TTL demultiplexer Pentium MMX 166 Processor MTC13 KLM-1 DTC20 mtc10 VT1536 MTD23 MTD27
Contextual Info: Intel IXF6151 28 T1/E1 Mapper Datasheet ® The Intel IXF6151 performs asynchronous mapping and demapping of 28 T1 and/or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface. Further

2x4 TTL demultiplexer

Contextual Info: Intel IXF6151 28 T1/E1 Mapper Datasheet The Intel® IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus

DTC24

Abstract: AU-AIS MTC27 vc-4 digital cross connect 226 35K 2x4 TTL demultiplexer Digital Alarm Clock by ttl Digital Alarm Clock by using ttl P03H GR-253-CORE
Contextual Info: IXF6151 28 T1/E1 Mapper Datasheet The IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/ or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface.

0221l

Abstract: APPLICATION NOTES CD 7474 IC bit-slice TGC119 TGC100 IPF 830 RC02X ci 7432 ttl DTN20 tsg 271
Contextual Info: TGC100 Series 1-|im CMOS Gate Arrays RELEASE 4.0. REVISED SEPTEMBER 1991 14 Arrays with up to 26K Available Gates C E LL C O LU M N Fast Prototype Turnaround Time W IR IN G C H A N N E L Extensive Design Support -Design Libraries Compatible With Valid,u and Mentor CAE Systems

X1HB

Abstract: telecom bus DM9000 application Digital Alarm Clock by using ttl LXT6251A 001H LXT6051 MTD10 LXT6282 MTC11
Contextual Info: LXT6251A 21 E1 SDH Mapper Datasheet The LXT6251A 21E1 Mapper performs asynchronous mapping and demapping of 21 E1 PDH signals into SDH. The PDH side interfaces with E1 LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard Telecom bus interface. Further processing by the companion