DS92LV1 Search Results

Contextual Info: DS92LV1260 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Literature Number: SNLS134E DS92LV1260 Six Channel 10 Bit BLVDS Deserializer General Description Features The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to

DS92LV18

Abstract: 2003120 ds92lv18tvv
Contextual Info: DS92LV18 DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz Literature Number: SNLS156D DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz General Description Features The DS92LV18 Serializer/Deserializer SERDES pair transparently translates a 18–bit parallel bus into a BLVDS serial

Contextual Info: DS92LV16 DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz Literature Number: SNLS138G DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz General Description Features The DS92LV16 Serializer/Deserializer SERDES pair transparently translates a 16–bit parallel bus into a BLVDS serial

DS92LV1023E

Abstract: 10-BIT
Contextual Info: DS92LV1023E [x 10 d in TCLK_R/F TCLK 30 MHz to 66 MHz PLL SYNC1 SYNC2 TIMING and CONTROL 10-Bit Deserializer

Contextual Info: DS92LV18 DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz Literature Number: SNLS156D DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz General Description Features The DS92LV18 Serializer/Deserializer SERDES pair transparently translates a 18–bit parallel bus into a BLVDS serial

Contextual Info: SN65LV1023A/SN65LV1224A 10ĆMHz TO 66ĆMHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS570D − JUNE 2003 − REVISED JANUARY 2005 D 100-Mbps to 660-Mbps Serial LVDS Data D D D Payload Bandwidth at 10-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

Contextual Info: SN65LV1023/SN65LV1224 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

Contextual Info: DS92LV1224 www.ti.com SNLS189 – APRIL 2005 DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer Check for Samples: DS92LV1224 FEATURES • 1 • 23 • • • 30–66 MHz Single 1:10 Deserializer with 300–660 Mb/s troughput Robust Bus LVDS serial data transmission

CON2x20

Abstract: 7476 feature of 7476 DS92LV18 DIN11 SCAN90CP02 SCAN921821 13V3 C4612 R49A
Contextual Info: 5 4 3 2 1 Reference schematic for redundant LVDS transmission D This schematic showcases an application for the following LVDS products by National Semiconductor: SCAN921821, SCAN90CP02, DS92LV18. Information and diagrams herein are provided for reference only. You

SLLS526D

Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526D – FEBRUARY 2002 – REVISED AUGUST 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

Contextual Info: SN65LV1023/SN65LV1224 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527A – FEBRUARY 2002 – REVISED APRIL 2002 D D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

SN65LVDS1023

Abstract: SN65LVDS1023DB SN65LVDS1224 SN65LVDS1224DB
Contextual Info: SN65LVDS1023/SN65LVDS1224 30 MHz TO 66 MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527 – FEBRUARY 2002 D D D 300–660 Mbps Serial LVDS Data Payload Bandwidth at 30 MHz to 66 MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224 Chipset Serializer/Deserializer Power

MO-150

Abstract: SN65LV1023 SN65LV1023DB SN65LV1224 SN65LV1224DB SN65LVDS1023 SN65LVDS1224 300Mbps
Contextual Info: SN65LV1023/SN65LV1224 30-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS527F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224

Contextual Info: DS92LV16 www.ti.com SNLS138H – JANUARY 2001 – REVISED APRIL 2013 DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz Check for Samples: DS92LV16 FEATURES DESCRIPTION • The DS92LV16 Serializer/Deserializer SERDES pair transparently translates a 16–bit parallel bus into a

LZ 02

Abstract: MO-150 SN65LV1021 SN65LV1021DB SN65LV1212 SN65LV1212DB SN65LVDS1021 SN65LVDS1212
Contextual Info: SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 D D D D 100-Mbps to 400-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 40-MHz System Clock Pin-Compatible Superset of NSM DS92LV1021/DS92LV1212

DS92LV1021

Abstract: DS92LV1210 MSA28 JRC 062
Contextual Info: PRELIMINARY Semiconductor S eptem ber 1998 DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer General Description The DS92LV1021 transform s a 10-bit w ide parallel C M O S/ TTL data bus into a single high speed Bus LVDS serial data

Contextual Info: DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery General Description Features The DS92LV1212A is an upgrade of the DS92LV1212. It maintains all of the features of the DS92LV1212. The DS92LV1212A is designed to be used with the DS92LV1021

Contextual Info: DS92LV1021, DS92LV1210 www.ti.com SNLS024B – MAY 2004 – REVISED MAY 2004 DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer Check for Samples: DS92LV1021, DS92LV1210 FEATURES 1 • Guaranteed transition every data transfer

AN-1217

Abstract: DS92LV16 DS92LV16TVHG VHG80A
Contextual Info: DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz General Description Features The DS92LV16 Serializer/Deserializer SERDES pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial

DS92LV1021

Abstract: DS92LV1210 DS92LV1212 DS92LV1212A
Contextual Info: DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery General Description Features The DS92LV1212A is an upgrade of the DS92LV1212. It maintains all of the features of the DS92LV1212. The DS92LV1212A is designed to be used with the DS92LV1021

Contextual Info: DS92LV1023E www.ti.com SNLS187A – MARCH 2005 – REVISED APRIL 2005 DS92LV1023E 30-66 MHz 10 Bit Bus LVDS Serializer Check for Samples: DS92LV1023E FEATURES • 1 • 23 • • • 30–66 MHz Single 10:1 Serializer with 300–660 Mb/s throughput Robust Bus LVDS serial data transmission

Contextual Info: DS92LV1260 www.ti.com SNLS134F – DECEMBER 2000 – REVISED APRIL 2013 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Check for Samples: DS92LV1260 FEATURES DESCRIPTION • The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS

Contextual Info: DS92LV1021, DS92LV1210 www.ti.com SNLS024C – MARCH 1999 – REVISED APRIL 2013 DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer Check for Samples: DS92LV1021, DS92LV1210 FEATURES DESCRIPTION • • The DS92LV1021 transforms a 10-bit wide parallel

lm1117 3.3V

Abstract: HDR3X2 BNC TO RJ45 WIRING diagram HDR10X2 DS92LV1021 DS92LV1212 LM1117 UVW generator machpro 1,1 mach schematic
Contextual Info: National Semiconductor DS92LV1021/DS92LV1212 Bus LVDS Serializer / Deserializer Demonstration Board with Pattern Generator/Checker National Semiconductor Bus LVDS SER/DES demo board – Rev 3.0 – 10/21/99 Table of Contents INTRODUCTION . 3