DS90UR241QVSX Search Results

Contextual Info: DS90UR124, DS90UR241 www.ti.com SNLS231M – SEPTEMBER 2006 – REVISED OCTOBER 2011 DS90UR241Q DS90UR124Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset Check for Samples: DS90UR124, DS90UR241 FEATURES 1 • • • 23 • •

DS90UR241IVS

Abstract: DS90UR241QVS DS90UR241QVSX RGB666 AEC-Q100 DS90C124
Contextual Info: September 4, 2009 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset General Description The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18bit color depth - RGB666 + HS, VS, DE + 3 additional general

RGB666

Abstract: LVDS connector 40 pins DS90C124 DS90UR124 giga media converter LVDS 30 pin connector cable LVDS connector 40 pins NAME SDI SERIALIZER SWITCHING NOISE SUPPRESSION OF LVDS SERIALIZER AEC-Q100
Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

AEC-Q100

Abstract: DS90UR241IVS DS90UR241QVS DS90UR241QVSX RGB666 DS90C124
Contextual Info: October 5, 2011 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset General Description The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18bit color depth - RGB666 + HS, VS, DE + 3 additional general

Contextual Info: DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 DS90UR124Q DS90UR241Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset Check for Samples: DS90UR124Q, DS90UR241Q FEATURES APPLICATIONS • • •

Contextual Info: DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 DS90UR124Q DS90UR241Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset Check for Samples: DS90UR124Q, DS90UR241Q FEATURES APPLICATIONS • • •

DS90C124

Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

DS90C124

Contextual Info: DS90UR124,DS90UR241 DS90UR241Q DS90UR124Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset Literature Number: SNLS231M October 5, 2011 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset General Description

DS90C124

Abstract: AEC-Q100 AN-1217 DS90UR124 DS90UR241 ISO10605
Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

Contextual Info: DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 DS90UR124Q DS90UR241Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset Check for Samples: DS90UR124Q, DS90UR241Q FEATURES APPLICATIONS • • •