DS844 Search Results

ACT 12.288

Contextual Info: CS2300-OTP Fractional-N Clock Multiplier with Internal LCO Features General Description  Clock Multiplier / Jitter Reduction The CS2300-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2300-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency

Holt an-300

Abstract: HI-8448-10 HI-8488-10 HI-8444 HI-8444PS HI-8444PS-10 HI-8445 HI-8448 HI-8444-10
Contextual Info: HI-8444, HI-8445, HI-8448 Quad / Octal ARINC 429 Line Receivers September 2006 PIN CONFIGURATIONS DESCRIPTION The HI-8444 and HI-8445 are quad ARINC 429 line receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers.

Holt an-300

Abstract: HI-8448 HI8448 HI-8448-10 HI-8445 Holt DO-160E HI-8444 HI-8444PS HI-8444PS-10
Contextual Info: HI-8444, HI-8445, HI-8448 Quad / Octal ARINC 429 Line Receivers May 2008 PIN CONFIGURATIONS DESCRIPTION The HI-8444 and HI-8445 are quad ARINC 429 line receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers.

HI8445PST-10

Contextual Info: HI-8444, HI-8445, HI-8448 Quad / Octal ARINC 429 Line Receivers January 2003 PIN CONFIGURATIONS DESCRIPTION The HI-8444 and HI-8445 are quad ARINC 429 line receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers.

CDK-2000-LCO

Abstract: CS2000 CS2300-OTP CS2300P-CZZ CS2300P-CZZR MO-187
Contextual Info: CS2300-OTP Fractional-N Clock Multiplier with Internal LCO Features General Description  Clock Multiplier / Jitter Reduction The CS2300-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2300-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency

Contextual Info: CS2300-OTP Fractional-N Clock Multiplier with Internal LCO Features General Description  Clock Multiplier / Jitter Reduction The CS2300-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2300-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency

DEI1044

Abstract: DEI1045 HI-8448 HI-8444 HI-8444PS HI-8445 HI-8445PS 8444pst HI-8444PST 8448PQT
Contextual Info: HI-8444, HI-8445, HI-8448 October 2001 PIN CONFIGURATIONS DESCRIPTION The HI-8444 and HI-8445 are quad ARINC 429 line receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers. The technology is analog / digital CMOS. The device is

HI-8448PS

Abstract: DO-160E Holt an-300 AN-300 HI-8444 HI-8444PS HI-8444PS-10 HI-8445 HI-8448 HI-84
Contextual Info: HI-8444, HI-8445, HI-8448 Quad / Octal ARINC 429 Line Receivers May 2010 PIN CONFIGURATIONS DESCRIPTION The HI-8444 and HI-8445 are quad ARINC 429 line receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers.

HI-8444-10

Abstract: DS8444
Contextual Info: HI-8444, HI-8445, HI-8448 Quad / Octal ARINC 429 Line Receivers March 2007 PIN CONFIGURATIONS DESCRIPTION The HI-8444 and HI-8445 are quad ARINC 429 line receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers.

Ablebond 84-1*SR4

Abstract: 0727 Ablebond 84-1LMISR4 QR-8009 DS8444
Contextual Info: Holt Integrated Circuits 23351 Madero Mission Viejo, CA 92691 PRODUCT CHANGE NOTIFICATION PCN PCN INFORMATION PCN # Title 0707 Qualification of “QFP” Package at CEI, Thailand Assembly Location for HI-8448PQxx-xx Date: 03/06/08 Date Effective: 09/01/07

Contextual Info: Confidential Draft 3/27/08 CS2300-OTP Fractional-N Clock Multiplier with Internal LCO Features General Description  Clock Multiplier / Jitter Reduction The CS2300-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock

CS2300-OTP

Abstract: CS2300P-CZZ CS2300P-CZZR MO-187 CDK-2000-LCO CS2000 ds844
Contextual Info: Confidential Draft 3/18/09 CS2300-OTP Fractional-N Clock Multiplier with Internal LCO Features General Description  Clock Multiplier / Jitter Reduction The CS2300-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock

HI-8444PSI-10

Abstract: HI8444PSI-10 HI8445PSI10 AN-300 HI-8444 HI-8444PS HI-8444PS-10 HI-8445 HI-8448 HI-8448-10
Contextual Info: HI-8444, HI-8445, HI-8448 Quad / Octal ARINC 429 Line Receivers January 2003 PIN CONFIGURATIONS DESCRIPTION The HI-8444 and HI-8445 are quad ARINC 429 line receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers.

8448PQI

Contextual Info: HI-8444, HI-8445, HI-8448 October 2001 PIN CONFIGURATIONS DESCRIPTION The HI-8444 and HI-8445 are quad ARINC 429 line receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers. The technology is analog / digital CMOS. The device is

DS8444

Contextual Info: HI-8444, HI-8445, HI-8448 Quad / Octal ARINC 429 Line Receivers October 2013 PIN CONFIGURATIONS DESCRIPTION The HI-8444 and HI-8445 are quad ARINC 429 line receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers.

44PTQS

Abstract: DS8444 HI-8444-10 ARINC Holt an-300
Contextual Info: HI-8444, HI-8445, HI-8448 Quad / Octal ARINC 429 Line Receivers February 2008 PIN CONFIGURATIONS DESCRIPTION The HI-8444 and HI-8445 are quad ARINC 429 line receiver ICs available in a 20-pin TSSOP package. The HI8448 contains 8 independent ARINC 429 line receivers.

CS2000

Abstract: CS2300-OTP CS2300P-CZZ CS2300P-CZZR MO-187 phase comparator
Contextual Info: CS2300-OTP Fractional-N Clock Multiplier with Internal LCO Features General Description  Clock Multiplier / Jitter Reduction The CS2300-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2300-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency