C 151 C
Abstract: LP2995M
Contextual Info: February 2002 LP2995 DDR Termination Regulator General Description Features The LP2995 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot
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LP2995
Abstract: LP2995LQ LP2995M LP2995MR LP2995MRX LP2995MX M08A 3a bus termination regulator psop
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The
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lp2995lp2995lqlp2995mlp2995mr+4lp2995mrxlp2995mxm08a3a bus termination regulator psop
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LP2995
Abstract: LP2995LQ LP2995M LP2995MR LP2995MRX LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The
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lp2995csp-9-111s2lp2995lqlp2995m+4lp2995mrlp2995mrxlp2995mxm08a
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LP2995
Abstract: LP2995LQ LP2995M LP2995MR LP2995MRX LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The
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psop-8
Abstract: 8 lead psop-8 NS package num. mra08a resistor 0,15 Ohm 5W DATA SHEET psop 44 northbridge Op amp circuit applications SSTL-2 5041c free circuit diagram of motherboard SO-8
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The
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lp2995csp-9-111c2csp-9-111s2psop-8+98 lead psop-8 ns package num. mra08aresistor 0,15 ohm 5w data sheetpsop 44northbridgeop amp circuit applicationssstl-25041cfree circuit diagram of motherboardso-8
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LP2955
Abstract: M08A LP2995
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。
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lp2995so-8psop-8llp-16ds200393-11-jpds200393+416-leadlqa16alp2955m08a
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northbridge
Abstract: LP2995 LP2995LQ LP2995LQX LP2995M LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients.
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LP2955
Abstract: LP2995 M08A SO-8PSOP-8LLP-16 LLP-16
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。
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LP2995M
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients.
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LP2995M
Abstract: LP2995 LP2995LQ LP2995MR LP2995MRX LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The
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lp2995lp2995mlp2995lqlp2995mr+3lp2995mrxlp2995mxm08a
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LP2995
Abstract: LP2995LQ LP2995LQX LP2995M LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients.
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