DS100288 Search Results

IXTA32P20T

Abstract: ixth32p20t IXTQ32P20T IXTP32P20T
Contextual Info: Preliminary Technical Information IXTA32P20T IXTP32P20T IXTQ32P20T IXTH32P20T TrenchPTM Power MOSFET P-Channel Enhancement Mode Avalanche Rated TO-263 AA IXTA VDSS ID25 RDS(on) TO-220AB (IXTP) G D S G DS S D (Tab) Symbol Test Conditions VDSS TJ = 25°C to 150°C

54AC273

Abstract: 74AC AC273 DS100288
Contextual Info: General Description Features The ’273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.

74ac logic

Contextual Info: 54AC273 54AC273 Octal D Flip-Flop Literature Number: SNOS104 General Description Features The ’273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input load and reset (clear) all

Contextual Info: + Semiconduc or 54AC273 Octal D Flip-Flop General Description Features The ’273 has e ight edge-triggered D-type flip-flops w ith indi­ vidual D inputs and Q o utputs. The com m on buffered C lock CP and M aster R eset (MR) input load and reset (clear) all

IXTH32P20T

Abstract: IXTA32P20T
Contextual Info: Advance Technical Information IXTA32P20T IXTP32P20T IXTH32P20T TrenchPTM Power MOSFET P-Channel Enhancement Mode Avalanche Rated VDSS ID25 = = ≤ RDS on - 200V - 32A Ω 130mΩ TO-263 AA (IXTA) G S D (Tab) TO-220AB (IXTP) Symbol Test Conditions Maximum Ratings

Contextual Info: Preliminary Technical Information TrenchPTM Power MOSFET P-Channel Enhancement Mode Avalanche Rated TO-263 AA IXTA VDSS ID25 IXTA32P20T IXTP32P20T IXTQ32P20T IXTH32P20T RDS(on) = = ≤ - 200V - 32A Ω 130mΩ TO-3P (IXTQ) TO-220AB (IXTP) G G D S D (Tab) G