DS00954 Search Results

74F524

Abstract: 74F524PC 74F524SC MS-001 MS-013
Contextual Info: Revised August 1999 74F524 8-Bit Registered Comparator General Description Features The 74F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are

54F413DM

Abstract: 74F413 74F413PC J16A N16E
Contextual Info: 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description Features The ’F413 is an expandable fall-through type high-speed First-In First-Out FIFO buffer memory organized as 64 words by four bits. The 4-bit input and output registers record

M20D

Abstract: MS-001 MS-013 74F373 74F533 74F533PC 74F533SC 74F533SJ
Contextual Info: Revised August 1999 74F533 Octal Transparent Latch with 3-STATE Outputs General Description Features The 74F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is

74F433

Abstract: 74F433SPC B255 N24C S9423
Contextual Info: Revised August 1999 74F433 First-In First-Out FIFO Buffer Memory General Description Features The 74F433 is an expandable fall-through type high-speed First-In First-Out (FIFO) Buffer Memory that is optimized for high-speed disk or tape controller and communication

524SC

Contextual Info: S E M IC O N D U C T O R T M 74F524 8-Bit Registered Comparator General Description allow tw os com plem ent as well as m agnitude com pare. Link­ ing inputs are provided fo r expansion to longer w ords. The ’F524 is an 8-bit bidirectional register with parallel input

Contextual Info: p PriM 9H 8!! iQ Q Q Revised A ugust 1999 E M IC O N D U C T G R T M 74F533 Octal Transparent Latch with 3-STATE Outputs General Description Features T h e 74F 533 consists o f eight latches with 3-STATE outputs for bus organized system applications. The flip-flops

Contextual Info: S E M IC O N D U C T O R tm 74F521 8-Bit Identity Comparator General Description Features The ’ F521 is an expandable 8-bit com parator. It com pares tw o w ords of up to e ight bits each and provides a LOW o ut­ put w hen th e tw o w ords match bit fo r bit. The expansion in­

Contextual Info: I R C H I I - D EMIC O N D U C T O R T 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description Features The ’F413 is an expandable fall-through type high-speed First-In First-O ut FIFO buffer m em ory organized as 64 w ords by fo u r bits. The 4-bit input and output registers record

CERAMIC LEADLESS CHIP CARRIER

Abstract: 54F533DM 74F533 74F533PC 74F533SC 74F533SJ F373 J20A M20D
Contextual Info: S E M IC O N D U C T O R tm 74F533 Octal Transparent Latch with 3-STATE Outputs General Description Features The ’F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is HIGH.

GT 1083

Abstract: 74F524 74F524PC 74F524SC F524 truth table for 4 bit magnitude comparator
Contextual Info: S E M IC O N D U C T O R tm 74F524 8-Bit Registered Comparator General Description allow tw os com plem ent as w ell as m agnitude com pare. Link­ ing inputs are provided for expansion to longer w ords. The ’F524 is an 8-blt bidirectional register with parallel input

54F413DM

Abstract: 74F413 74F413PC DSO09541-2 J16A N16E
Contextual Info: S E M IC O N D U C T O R tm 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description Features The ’F413 is an expandable fall-through type high-speed First-In First-O ut FIFO buffer m em ory organized as 64 w ords by four bits. The 4-bit input and output registers record

74F533

Abstract: 54F533DM 54F533FM 54F533LM 74F533PC 74F533SC 74F533SJ F373 F533
Contextual Info: 74F533 Octal Transparent Latch with 3-STATE Outputs General Description Features The ’F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is HIGH.

74F524

Abstract: 74F524PC 74F524SC F524
Contextual Info: 74F524 8-Bit Registered Comparator General Description The ’F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines S0, S1 to execute shift, load,

74F534

Abstract: 74F374 74F534PC 74F534SC 74F534SJ M20D MS-001 MS-013
Contextual Info: Revised October 2000 74F534 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The 74F534 is a high speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered

Contextual Info: p P r iM 9 H 8 ! ! iQ Q Q R e v is e d A u g u s t 1 9 9 9 EMICONDUCTGRTM 74F534 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features T h e 7 4 F 5 3 4 is a h ig h s p e e d , lo w -p o w e r o c ta l D -ty p e flip - • E d g e -trig g e re d D -ty p e in p u ts

Contextual Info: / M R C H I I - D S E M IC O N D U C T O R tm 74F534 Octal D-Type Flip-Flop with -STATE Outputs General Description Features T h e ’F 5 3 4 is a h ig h s p e e d , io w -p o w e r o c ta l D -ty p e flip -flo p • E d g e -trig g e re d D -ty p e in p u ts

74F413

Abstract: 74F413PC MS-001 N16E
Contextual Info: Revised August 1999 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description Features The F413 is an expandable fall-through type high-speed First-In First-Out FIFO buffer memory organized as 64 words by four bits. The 4-bit input and output registers

fairchild 9423

Abstract: irf 44 n 74F433 74F433SPC F433 N24C IRF 260 N fifo 9423
Contextual Info: 74F433 First-In First-Out FIFO Buffer Memory General Description Features The ’F433 is an expandable fall-through type high-speed first-in first-out (FIFO) buffer memory that is optimized for high-speed disk or tape controller and communication buffer

PIC Light Dimmer

Abstract: x10 pic an236 zero crossing detector PIC dimmer TRIAC dimmer pic PIC18F452 PWM example codes interfacing of PIC16F877A with 2X16 lcd pic triac PIC16F877A 2x16 LCD PWM GENERATION using Pic16F877A PIC16F877A circuit diagram
Contextual Info: AN236 X-10 Home Automation Using the PIC16F877A Author: HARDWARE OVERVIEW Jon Burroughs Microchip Technology Inc. The home controller application described in this application note allows the user to program on and off times for up to sixteen devices, using a 2 x 16 liquid crystal

74F521

Abstract: 54F521DM 74F521MSA 74F521PC 74F521SC 74F521SJ F521 J20A
Contextual Info: 74F521 8-Bit Identity Comparator General Description Features The ’F521 is an expandable 8-bit comparator. It compares two words of up to eight bits each and provides a LOW output when the two words match bit for bit. The expansion input IA=Balso serves as an active LOW enable input.

74F373

Abstract: 74F533 74F533PC 74F533SC 74F533SJ M20D MS-001 MS-013
Contextual Info: Revised October 2000 74F533 Octal Transparent Latch with 3-STATE Outputs General Description Features The 74F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is

Contextual Info: S E M Revised A ugust 1999 I C O N D U C T O R TM 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description Features The F413 is an expandable fall-through type high-speed First-In First-O ut FIFO buffer m em ory organized as 64

Contextual Info: S E M IC O N D U C T O R tm 74F533 Octal Transparent Latch with 3-STATE Outputs General Description Features The ’ F533 consists of e ight latches w ith 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data w hen Latch Enable LE is HIGH.

Contextual Info: A I R C H I L D S E M I C O N D U C T O R TM 74F433 First-In First-Out FIFO Buffer Memory General Description Features T h e ’ F 4 3 3 is a n e x p a n d a b le fa ll-th ro u g h ty p e h ig h -s p e e d • S e ria l o r p a ra lle l in p u t firs t-in firs t-o u t (F IF O ) b u ffe r m e m o ry th a t is o p tim iz e d fo r