DS00947 Search Results

74f132 national

Abstract: 54F132DM 54F132FM 54F132LM 74F132PC F132 J14A M14A M14D N14A
Contextual Info: General Description The ’F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In

74F86

Contextual Info: Revised July 1999 74F86 2-Input Exclusive-OR Gate General Description This device contains four independent gates, each of which performs the logic exclusive-OR function. Ordering Code: Order Number Package Number Package Description 74F86SC M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150 Narrow

1 into 12 demultiplexer circuit diagram

Abstract: 1 into 4 demultiplexer circuit diagram 74f139 1 into 16 demultiplexer circuit diagram Truth table of 1 to 16 demultiplexer
Contextual Info: 74F139 Dual 1-of-4 Decoder/Demultiplexer April 1988 Revised July 1999 74F139 Dual 1-of-4 Decoder/Demultiplexer General Description Features The F139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive

74F86

Abstract: 74F86PC 74F86SC 74F86SJ M14A M14D N14A
Contextual Info: 74F86 2-Input Exclusive-OR Gate General Description This device contains four independent gates, each of which performs the logic exclusive-OR function. Ordering Code: Commercial Package Package Description Number 74F86PC N14A 14-Lead 0.300" Wide Molded Dual-in-Line

74F132

Abstract: 74F132PC 74F132SC 74F132SJ F132 M14A M14D MS-001 N14A
Contextual Info: Revised July 1999 74F132 Quad 2-Input NAND Schmitt Trigger General Description The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output

Contextual Info: E M IC O N D U C T Q R t 74F132 Quad 2-Input NAND Schmitt Trigger General Description The F132 contains fo u r 2-input NAND gates w hich accept standard TT L input signals and provide standard T T L output levels. T hey are capable of transform ing slow ly changing in­

a215c

Abstract: 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
Contextual Info: A p riM 9 8 8 Revised January 1999 74F109^ Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to Cp sets Q to LOW level T he F 1 09 consists of tw o high-speed, com pletely indepen­ dent transition clocked JK flip-flops. The clocking operation

74F113

Abstract: 74F113PC 74F113SC 74F113SJ M14A M14D MS-001 N14A
Contextual Info: Revised July 1999 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as

ECG SEMICONDUCTOR DATA BOOK

Abstract: Li-ion charger controller sot23-5 Li-ion sot23-5 MCP73831 DS00971 ECG circuit diagram DS21984 DS00947 purpose of 2.2 kilo ohm resistor ERJ-3EK1002V
Contextual Info: MCP73831 Evaluation Board User’s Guide 2005 Microchip Technology Inc. DS51596A Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet.

Contextual Info: S E M IC O N D U C T O R tm 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description Asynchronous input: The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be

54F109DM

Abstract: 54F109FM 54F109LM 74F109PC F109 J16A M16A M16D N16E 74F109
Contextual Info: LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH General Description The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation

74F112

Contextual Info: E M I R ¡ C O C H April 1988 I L D N D U C T O Revised July 1999 R TM 74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description Simultaneous LOW signals on S q and C q force both Q and The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state

Contextual Info: R C H I I _ D E M IC O N D U C T O R t 74F139 Dual 1-of-4 Decoder/Demultiplexer General Description The F 13 9 is a Features h ig h -s p e e d , dual 1 -o f-4 d e c o d e r/ • M u ltifu n c tio n c a p a b ility d e m u ltip le x e r. T h e d e v ic e ha s tw o in d e p e n d e n t d e c o d e rs ,

74f132 national

Contextual Info: The ’F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional

Contextual Info: S E M IC O N D U C T O R tm 74F132 Quad 2-Input NAND Schmitt Trigger General Description The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing in­

Contextual Info: S E M IC O N D U C T O R tm 74F125 Quad Buffer 3-STATE Features • High impedance base inputs for reduced loading Ordering Code: Com m ercial Package Package D escription Number 74F125PC N14A 14-Lead (0.300" Wide) Molded Dual-In-Line 74F125SC (Note 1) M14A

74F138

Abstract: F138 1 into 4 demultiplexer circuit diagram 1 into 12 demultiplexer circuit diagram 74F138PC 74F138SC 74F138SJ M16A M16D MS-001
Contextual Info: Revised September 2000 74F138 1-of-8 Decoder/Demultiplexer General Description Features The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables

74F109

Abstract: F109 74F109PC 74F109SC 74F109SJ M16A M16D MS-001 N16E 74f109 fairchild
Contextual Info: Revised September 2000 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.

1 into 4 demultiplexer circuit diagram

Abstract: 74F139 circuit of 1-8 demultiplexer 74F139PC 74F139SC 74F139SJ F139 M16A M16D MS-001
Contextual Info: Revised September 2000 74F139 Dual 1-of-4 Decoder/Demultiplexer General Description Features The F139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive

74F132SC

Abstract: 74F132 74F132PC 74F132SJ F132 M14A M14D MS-001 N14A
Contextual Info: Revised September 2000 74F132 Quad 2-Input NAND Schmitt Trigger General Description The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output

74F138

Abstract: F138 74F138PC 74F138SC 74F138SJ M16A M16D N16E
Contextual Info: 74F138 1-of-8 Decoder/Demultiplexer General Description Features The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138

74F125

Abstract: 74F125PC 74F125SC 74F125SJ M14A M14D MS-001 N14A
Contextual Info: Revised July 1999 74F125 Quad Buffer 3-STATE Features • High impedance base inputs for reduced loading Ordering Code: Order Number Package Number Package Description 74F125SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

74F86

Abstract: 74F86PC 74F86SC 74F86SJ M14A M14D MS-001 N14A
Contextual Info: Revised July 1999 74F86 2-Input Exclusive-OR Gate General Description This device contains four independent gates, each of which performs the logic exclusive-OR function. Ordering Code: Order Number Package Number Package Description 74F86SC M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150 Narrow

74F109

Abstract: 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
Contextual Info: Revised January 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to CD sets Q to LOW level The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.