DS00588 Search Results

MM74C48N

Abstract: BCD-TO-7-SEGMENT DECODER 11 pin 7 segment filament MM74C48 MS-001 N16E
Contextual Info: Revised January 1999 MM74C48 BCD-to-7 Segment Decoder General Description Features The MM74C48 BCD-to-7 segment decoder is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Seven NAND gates and one driver are connected in pairs

Contextual Info: s e m ic o n d u c t o r Revised Ja nuary 1999 MM74C89 64-Bit 3-STATE Random Access Read/Write Memory General Description A ddress O peration: Address inputs must be stable tsA prior to the positive to negative transition of m em ory enable. It is thus not necessary to hold address inform ation

200B

Abstract: AN588 NC38 PIC16C5X PIC17CXXX RG41 disc Piezoelectric crystal
Contextual Info: AN588 PICmicro Microcontroller Oscillator Design Guide Design Challenges Author: Kim Peck Consultant Designing a clock oscillator without some knowledge of the fundamental principals of acoustic resonators is possible but fraught with the uncertainty of "cut and try"

Contextual Info: R e v is e d J a n u a ry 199 9 S E M I C D N D U C T D R tm MM74C89 64-Bit 3-STATE Random Access Read/Write Memory General Description Read O peration: T h e c o m p le m e n t o f th e in fo rm a tio n w h ic h w a s w ritte n in to th e m e m o ry is n o n -d e s tru c tiv e ly

74L85

Abstract: AN-90 MM74C85 MM74C85N MS-001 N16E
Contextual Info: O ctober 1987 Revised January 1999 S E M IC O N D U C TO R T M MM74C85 4-Bit Magnitude Comparator General Description V|N(1 applied to the A = B input and low level voltage T he M M 74C 85 is a four-bit m agnitude com parator which will perform com parison o f straight binary or BCD codes.

AN-90

Abstract: M14A MM74C86 MM74C86M MM74C86N MS-001 N14A MM74LS
Contextual Info: Revised January 1999 MM74C86 Quad 2-Input EXCLUSIVE-OR Gate General Description Features The MM74C86 employs complementary MOS CMOS transistors to achieve wide power supply operating range, low power consumption and high noise margin these gates provide basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel

AN-90

Abstract: MM74C90 MM74C93 MM74C93N MS-001 N14A
Contextual Info: Revised January 2004 MM74C93 4-Bit Binary Counter General Description Features The MM74C93 binary counter and complementary MOS CMOS integrated circuits constructed with N- and Pchannel enhancement mode transistors. The 4-bit binary counter can be reset to zero by applying high logic level on

AN-90

Abstract: MM74C42 MM74C42N MS-001 N16E
Contextual Info: Revised May 2002 MM74C42 BCD-to-Decimal Decoder General Description Features The MM74C42 one-of-ten decoder is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. This decoder produces a logical “0” at the output corresponding to a four

AN-90

Abstract: DM7489 MM74C89 MM74C89N MS-001 N16E
Contextual Info: Revised May 2002 MM74C89 64-Bit 3-STATE Random Access Read/Write Memory General Description Features The MM74C89 is a 16-word by 4-bit random access read/ write memory. Inputs to the memory consist of four address lines, four data input lines, a write enable line and a memory enable line. The four binary address inputs are

Contextual Info: A I R C H I L D Revised January 1999 S E M I C D N D U C T D R tm MM74C42 BCD-to-Decimal Decoder General Description • Low pow er: The M M 74C 42 one-of-ten decoder is a m onolithic com ple­ m entary MOS C M O S integrated circuit constructed with N- and P-channel e nhancem ent transistors. This decoder

74C85

Contextual Info: O ctober 1987 Revised Ja nuary 1999 SEMICONDUCTOR!!^ MM74C85 4-Bit Magnitude Comparator General Description V|N (i applied to the A = B input and low level voltage (V|N(o) applied to A > B and A < B inputs. Features • W ide supply voltage range: ■ G uaranteed noise m argin:

Contextual Info: O ctober 1987 Revised January 1999 S E M I C O N D U C T O R TM MM74C74 Dual D-Type Flip-Flop General Description • High noise im m unity: The M M 74C 74 dual D-type flip-flop is a m onolithic com ple­ m entary MOS C M O S integrated circuit constructed with

74C93N

Abstract: IC 74C90 74C90N of CMOS IC 74c90 74C90 74C93
Contextual Info: A I R C H I L D R e v is e d J a n u a ry 199 9 S E M IC D N D U C T O R tm MM74C90 • MM74C93 4-Bit Decade Counter • 4-Bit Binary Counter General Description to o p e ra te it a s a d iv id e -b y -2 , -8 , o r -1 6 d iv id e r. C o u n tin g o c c u rs on th e n e g a tiv e g o in g e d g e o f th e in p u t pu ls e .

Contextual Info: O c to b e r 198 7 R e v is e d J a n u a ry 1 9 9 9 SEMICONDUCTOR!!^ MM74C48 BCD-to-7 Segment Decoder General Description Features T h e M M 7 4 C 4 8 B C D -to -7 s e g m e n t d e c o d e r is a m o n o lith ic • W id e s u p p ly v o lta g e ra n g e :

AN-90

Abstract: MM74C90 MM74C90N MM74C93 MM74C93N MS-001 N14A
Contextual Info: s e m ic o n d u c t o r Revised January 1999 MM74C90 • MM74C93 4-Bit Decade Counter • 4-Bit Binary Counter General Description to operate it as a divide-by-2, -8, or -16 divider. Counting occurs on the negative going edge of the input pulse. T he M M 74C 90 decade counter and the M M 74C 93 binary

AN-90

Abstract: M14A MM74C32 MM74C32M MM74C32N MS-001 N14A
Contextual Info: Revised January 1999 MM74C32 Quad 2-Input OR Gate General Description The MM74C32 employs complementary MOS CMOS transistors to achieve low power and high noise margin, these gates provide the basic functions used in the implementation of digital integrated circuit systems. The N- and

MM74C73N

Abstract: MM74C73 MM74C76N datasheet M16A MM74C76 MM74C76M MM74C76N MS-001 N14A N16E
Contextual Info: Revised January 1999 MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset General Description Features The MM74C73 and MM74C76 dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement transistors.

DS00588

Abstract: pic code for sine wave inverter pic based sine wave inverter sine wave inverter using pic pic sine inverter 200B DK-2750 FACT001 PIC16C71 sine wave inverter pic
Contextual Info: M FACT001 Basic PIC16/17 Oscillator Design FIGURE 1: Author: Dan Matthews Microchip Technology Inc. The oscillator circuit is one of the most overlooked areas of microprocessor circuit design. Components are usually selected based on the manufacturers’ tables. If the circuit starts up and works, fine, no other

AN-90

Abstract: DM7489 MM74C89 MM74C89N MS-001 N16E
Contextual Info: Revised January 1999 MM74C89 64-Bit 3-STATE Random Access Read/Write Memory General Description The MM74C89 is a 16-word by 4-bit random access read/ write memory. Inputs to the memory consist of four address lines, four data input lines, a write enable line and a memory enable line. The four binary address inputs are

74L85

Abstract: 3 bit magnitude comparator MM74C85N truth table for 4 bit magnitude comparator AN-90 MM74C85 MS-001 N16E
Contextual Info: Revised January 1999 MM74C85 4-Bit Magnitude Comparator General Description The MM74C85 is a four-bit magnitude comparator which will perform comparison of straight binary or BCD codes. The circuit consists of eight comparing inputs A0, A1, A2, A3, B0, B1, B2, B3 , three cascading inputs (A > B, A < B

74C86

Contextual Info: O c to b e r 198 7 R e v is e d J a n u a ry 1 9 9 9 S E M IC O N D U C T O R !!^ MM74C86 Quad 2-Input EXCLUSIVE-OR Gate General Description The M M 74C 86 Features e m p lo y s c o m p le m e n ta ry MOS C M O S tra n s is to rs to a c h ie v e w id e p o w e r s u p p ly o p e ra tin g range,

MM74C73n

Abstract: mm74c73
Contextual Info: A I R C H I L D O ctober 1987 Revised January 1999 SEMICONDUCTOR TM MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset General Description Features The M M 74C 73 and M M 74C 76 dual J-K flip-flops are m ono­ lithic com plem entary MOS CMOS integrated circuits con­

MM74C48N

Abstract: MM74C48 BCD-TO-7-SEGMENT MS-001 N16E
Contextual Info: Revised May 2002 MM74C48 BCD-to-7 Segment Decoder General Description Features The MM74C48 BCD-to-7 segment decoder is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Seven NAND gates and one driver are connected in pairs

z cut quartz piezoelectric properties

Abstract: disc Piezoelectric crystal 28 MHZ crystal oscillator resonator capacitor resistor dielectric resonator oscillator high frequency arc welding schematic oscillator coupled resonator amplifier phase shift oscillator phase shift resistance welding PIC microcontroller 3 phase
Contextual Info: AN588 PICmicro Microcontroller Oscillator Design Guide Design Challenges Author: Kim Peck Consultant Designing a clock oscillator without some knowledge of the fundamental principals of acoustic resonators is possible but fraught with the uncertainty of "cut and try"