DS0034 Search Results

FPGA Virtex 6 pin configuration

Abstract: Virtex CS144 TQ144 XCV100 XCV150 XCV200 XCV300 XCV50 xapp151
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R 3 Architectural Description The output buffer and all of the IOB control signals have independent polarity controls. VersaRing The Virtex architecture also includes the following circuits that connect to the GRM.

LUCL9214GAU-DT

Abstract: TGS 308 TGS2400 342AL
Contextual Info: Preliminary Data Sheet October 2000 L9214A/G Low-Cost Ringing SLIC Introduction Applications The L9214 is a subscriber line interface circuit that is optimized to provide a very low-cost solution for short- and medium-loop applications. This device provides the complete set of line interface functionality, including power ringing needed to interface to a

MM4220DF/MM5220DF

Abstract: mm5221 MM4240 DS8807 MM5017 54S287 MM1402a equivalent transistor bf 175 MM74C920 MM5061
Contextual Info: Edge Index by Product Family NATIONAL This is National's first Memory handbook containing information on MOS and Bipolar Memory Components, Systems, Application Notes and Support Circuits. For detailed information on Interface Circuits and other major product lines, contact a National sales office, representative, or distributor.

l9214

Abstract: GR-909 L9214A L9214G MO-220 T7504 T8536 rgn 1064 agere 840
Contextual Info: Preliminary Data Sheet October 2001 L9214A/G Low-Cost Ringing SLIC Introduction Applications The Agere Systems Inc. L9214 is a subscriber line interface circuit that is optimized to provide a very low-cost solution for short- and medium-loop applications. This device provides the complete set of line

microtek inverter circuit

Abstract: SST28F040 data circuit schematics satellite connector PMC3370 u34 c634 12vdc to 120vac inverter schematic diagram smd diode L48 R735-R738 DS1834AS smd diode code L49
Contextual Info: PM3575 APPLICATION NOTE PMC-981057 ISSUE 1 EXACT 24+2 REFERENCE DESIGN PM3575 EXACT 24 x 10/100 + 2 x 1000 ETHERNET SWITCH REFERENCE DESIGN ISSUE 1: FEBRUARY 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PM3575

XCV300

Abstract: XCV150 XCV100 XCV1000 XCV200 XCV400 XCV50 XCV600 XCV800 xcv300 pin information
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-3 v3.0 February 1, 2002 3 Product Specification Virtex Electrical Characteristics Definition of Terms Electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,

Contextual Info: Data Sheet February 2001 A1751A DWDM Analog Forward-Path or Return-Path Laser Modules Description The A1751A laser module is a dense wavelengthdivision multiplexing DWDM laser for analog applications. It features a distributed-feedback (DFB) chip that has been designed specifically for radio frequency (RF) applications. The A1751A laser module

Virtex

Abstract: XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600 XCV800
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-3 v3.2 September 10, 2002 Production Product Specification Virtex Electrical Characteristics Definition of Terms Electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,

Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-3 v3.1 July 19, 2002 3 Production Product Specification Virtex Electrical Characteristics Definition of Terms Electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,

ds003

Abstract: Field Programmable Gate Arrays 512 552 XCV200 FPGA Virtex 6 pin configuration XCV1000 XCV150 XCV300 XCV400 XCV600
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v2.5 April 2, 2001 3 Product Specification Features • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz

XCV100 TQ144

Abstract: DS0034 XCV600 XCV800 ip108 DS003 AD 149 AE9 diode t25 4 L9 XCV200 TQ144
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-4 v2.7 July 19, 2001 3 Product Specification Virtex Pin Definitions Table 1: Special Purpose Pins Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 Yes Input Clock input pins that connect to Global Clock Buffers. These pins become

XCV100

Abstract: XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600 XCV800
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-3 v2.9 October 29, 2001 3 Product Specification Virtex Electrical Characteristics Definition of Terms Electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as Advance,

Contextual Info: Product Obsolete/Under Obsolescence Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v4.0 March 1, 2013 Product Specification Features • • • • • Fast, high-density Field Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz

fm transmitter 10 KM

Abstract: Forward Path Laser Transmitter Module Diagram A1751A qam laser transmitter QAM schematic diagram agere photodiode
Contextual Info: Data Sheet, Rev. 3 April 2001 A1751A DWDM Analog Forward-Path or Return-Path Laser Modules Description The A1751A laser module is a dense wavelengthdivision multiplexing DWDM laser for analog applications. It features a distributed-feedback (DFB) chip that has been designed specifically for radio frequency (RF) applications. The A1751A laser module

ds003

Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-3 v2.5 April 2, 2001 3 Product Specification Virtex Electrical Characteristics Definition of Terms Data sheets can be designated as Advance or Preliminary. The status of specifications in these data sheets is as follows:

PerkinElmer Optoelectronics

Abstract: PerkinElmer transformer TR130 opto 611 TR-130 lb716
Contextual Info: 24" M I N 6 0 9 . (T YP ) T PS #28 W H #28 YEL PF # 28 RE D S F DIM ENSIONS ARE IN INCHES (M ILLIM ETERS) 11/16 (17.5) M AX. ABCRD # 28 BLK SS TR-130 EXTERNALTRIGGER TRANSFORMER 3/32 (2.4) M IN. W EIGHT = 0.02 LB 7/16 (11.1) M AX. OUTLINE DIMENSIONS SPECIFICATIONS

lucent m12 timing receiver

Contextual Info: Advance Data Sheet August 2000 TRCV0110G 10 Gbits/s Clock Recovery, 1:16 Data Demultiplexer Features • Fully-integrated clock recovery, 1:16 data demultiplexer ■ Supports the standard OC-192/STM-64 data rate of 9.9532 GHz as well as the FEC rate of 10.6642 GHz

fm transmitter 10 KM

Abstract: A1751A Forward Path Laser Transmitter Module Diagram agere photodiode
Contextual Info: Data Sheet March 2001 A1751A DWDM Analog Forward-Path or Return-Path Laser Modules Description The A1751A laser module is a dense wavelengthdivision multiplexing DWDM laser for analog applications. It features a distributed-feedback (DFB) chip that has been designed specifically for radio frequency (RF) applications. The A1751A laser module

XCV100

Abstract: XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600 XCV800 xapp151
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v2.5 April 2, 2001 3 Product Specification Features • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz

XCV100 TQ144

Abstract: AF3 din 74 k11 zener diode XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v2.5 April 2, 2001 3 Product Specification Features • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz

XCV100 TQ144

Abstract: ds003 diode t25 4 L9 XCV400 XCV50 XCV600 XCV800 CS144 TQ144 DS0034
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-4 v2.8 July 19, 2002 Production Product Specification Virtex Pin Definitions Table 1: Special Purpose Pins Dedicated Pin Direction Description GCK0, GCK1, GCK2, GCK3 Yes Input Clock input pins that connect to Global Clock Buffers. These pins become

schematic diagram online UPS

Abstract: CS144 TQ144 XCV100 XCV150 XCV200 XCV300 XCV50 DS003
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R Architectural Description The output buffer and all of the IOB control signals have independent polarity controls. VersaRing The Virtex architecture also includes the following circuits that connect to the GRM.

FPGA Virtex 6 pin configuration

Abstract: Field Programmable Gate Arrays XCV100 TQ144 XCV400 676 package drawing 512 552 CS144 Virtex XCV100 XCV1000 XCV150
Contextual Info: Virtex 2.5 V Field Programmable Gate Arrays R DS003-1 v2.5 April 2, 2001 Product Specification Features • • • • • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz - 66-MHz PCI Compliant

TTRN0110G

Abstract: D10GP 198-pin
Contextual Info: Advance Data Sheet August 2000 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Features • Fully-integrated 10 GHz clock synthesizer; 16:1 data multiplexer ■ Supports standard OC-192/STM-64 data rate of 9.9532 GHz as well as FEC rate of 10.6642 GHz