DRAM CONTROLLER 25 MHZ Search Results

74LS764

Abstract: logic diagram and symbol of DRAM 74LS N74LS764A N74LS764N PLCC-44 18-BlT LS764
Contextual Info: 74LS764 Signetics DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh

74LS764

Abstract: LS764
Contextual Info: 74LS764 Signetics DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh

74ls

Abstract: N74LS764N
Contextual Info: Signelics 74LS764 DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL • Replaces 25 TTL devices to

A1266

Abstract: 16KX8 74LS 74LS764 N74LS764A N74LS764N PLCC-44
Contextual Info: 74LS764 S ignetics DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh

82425EX

Abstract: 82426EX 82420 82420EX t34i osa-104 AA T37B t17c tag044 82C42
Contextual Info: 82420EX PCISET DATA SHEET 82425EX PCI SYSTEM CONTROLLER PSC AND 82426EX ISA BRIDGE (IB) Y Y Y Y Host CPU 25 – 33 MHz Intel486 TM and OverDrive TM Processors L1 Write-Back Support Integrated DRAM Controller 1 to 128 MByte Main Memory 70 ns Fast Page Mode DRAM SIMMs

P16R6

Contextual Info: in t e i AP-704 APPLICATION NOTE A Simple DRAM Controller for 25/16 MHz i960 CA/CF Microprocessors F e b r u a ry 2 0 , 1995 I Order Number: 272628-001 1-499 intei 1.0 INTRODUCTION T his application note describes a sim ple DRAM controller for use with 25 and 16 M H z i960® Cx processors. O ther

MSL9350

Abstract: 80386dx pipeline sl9350 via sl9350 via flexset
Contextual Info: SL9350 80386DX Page Mode Memory Controller PRELIMINARY FEATURES • Supports 80386DX based AT Designs. • Up to 25 MHz Performance. • Enhanced Fast Page Mode DRAM Controller. • Supports 16 M byte of on Board Memory. • Shadow RAM Feature. • Programmable Wait State Options.

logical block diagram of 80286

Abstract: TL4A A20GATE sl93 sl90 LIM EMS 4.0 SL9151
Contextual Info: SL9151 80286 Page Interleave Memory Controller PRELIMINARY FEATURES • Supports 80286 based designs. • 16,20 or 25 MHz Options. • Enhanced Fast Page Mode/Page Interleave DRAM Controller. • Hardware support for EMS LIM 4.0 standard and EEMS. • Supports up to 8 M byte of on board memory.

simple heart rate monitor circuit diagram

Abstract: amd 29030 VF132A AA10 C1995 NSBMC292 NSBMC292-16 NSBMC292VF V292BMC 11806 equivalent
Contextual Info: NSBMC292 TM -16 -25 -33 Burst Memory Controller General Description The NSBMC292 Burst Memory Controller is an integrated circuit which implements all aspects of DRAM control for high performance systems using an Am29030TM or Am29035 Processor The NSBMC292 is functionally equivalent to the V292BMC TM

AA10

Abstract: C1995 NSBMC096 NSBMC096-16 NSBMC096VF V96BMC VF132A
Contextual Info: NSBMC096-16 -25 -33 Burst Memory Controller General Description The NSBMC096 Burst Memory Controller is an integrated circuit which implements all aspects of DRAM control for high performance systems using an i960 CA CF SuperScalar Embedded Processor The NSBMC096 is functionally equivalent to the V96BMC TM

p22v10.dev

Abstract: altera epx740 P16R6 p20v8r.dev 74F258 p22v10 74F245 EPX740 AP-704
Contextual Info: A AP-704 APPLICATION NOTE A Simple DRAM Controller for 25/16 MHz i960 CA/CF Microprocessors Rick Schue ® i960 Microprocesor Architecture Specialist Intel Corporation Embedded Processor Division Mail Stop CH5-233 5000 W. Chandler Blvd. Chandler, Arizona 85226

Contextual Info: UNITE» MICROELECTRONICS UM82C388 3QE D • ^355655 DOD01 fab 1 5^-33 ^ \ INTEL Cache Interface Features ■ Supports 16 MHz, 20 MHz and 25 MHz Intel 80386 Supports 2 5 6 K and 1M DRAM S ■ Supports 25 MHz 80386 with 82385 cache controller 1.2/it CMOS technology

microCMOS Programmable Dynamic RAM Controller

Abstract: DP84412 C1995 DP8440 DP8440-25 DP8440-40 DP8440V-40 DP8441 DP8441-25 DP8441-40
Contextual Info: DP8440-40 DP8440-25 DP8441-40 DP8441-25 microCMOS Programmable 16 64 Mbit Dynamic RAM Controller Driver General Description Features The DP8440 41 Dynamic RAM Controllers provide an easy interface between dynamic RAM arrays and 8- 16- 32- and 64-bit microprocessors The DP8440 41 DRAM Controllers

IMSB417

Abstract: T800 inmos static ram
Contextual Info: Chapter 23 189 IMS B417 TRAM 32-bit transputer 4 Mbytes Size 4 m os Engineering Data Reset Analyse NotError Terminated links Subsystem. PAL FEATURES IMS T800 25 MHz Transputer 64 Kbytes of zero wait-state SRAM 4 Mbytes of single wait-state DRAM Subsystem controller circuitry

82424TX

Abstract: 82424 82423 487 SX "snoop filter" Intel486DX2 rde l2 40 82424ZX
Contextual Info: intei 82424 CACHE AND DRAM CONTROLLER CDC • Supports 25 MHz/33 MHz/50 MHz Intel486 SX, l n t e l 4 8 7 TM SX, Intel486 DX, Intel486 DX2, O v e r D r i v e ™ for Intel486 and OverDrive for DX2 Processors ■ Fully Synchronous, 25 MHz/33 MHz PCI Bus Capable of Supporting Bus

schematic 80386

Abstract: e174 ALS6311 80386 microprocessor PAL20R4D AN619 DP8421A C1995 DP8420A DP8422A
Contextual Info: National Semiconductor Application Note 619 Lawson H C Chang February 1989 INTRODUCTION This application note describes how to interface the 80386 microprocessor to the DP8422A DRAM controller also applicable to DP8420A 21A with burst mode access The 80386 is running at 16 MHz 20 MHz or 25 MHz speed It is

Winsystems

Abstract: AN/Winsystems "Keyboard Controller" Intel386 floppy disk interface B 817 c PC computer board
Contextual Info: SINGLE BOARD COMPUTERS WINSYSTEMS MCM-SX STD Bus SBC • ■ ■ ■ ■ ■ ■ ■ ■ ■ 25 MHz Intel386 Processor With Up to 16 MB DRAM Small: 4.5" x 6.5" Onboard Solid State Disk Storage COM1, COM2, and LPT Ports IDE and Floppy Disk Interface AT Keyboard Controller and

80486 interface with keyboard

Abstract: m027 80486 m029 laptop motherboard block diagram AT40493 8042 Keyboard Controller M010 RAM Cache control logic burst controller coprocessor
Contextual Info: AT40493/392 Features • Two-Chip PC/AT Compatible Chip Set «or 80486 Based Systems Operating up to 50 MHz AT40493 System and Cache Controller AT40392 Data Buffer Controller Two 160-Pln Quad Flatpacks On-Chip Support for Direct-Mapped Write-Back Cache 0 Wait State Cache Read Hit and Programmable 0/1 Walt State

Programmable logic controller

Contextual Info: AT40493/392 Features • • • • • • • • • • • • • • • • • • • Two-Chip PC/AT Compatible Chip Set for 80486 Based Systems Operating up to 50 MHz AT40493 System and Cache Controller AT40392 Data Buffer Controller Two 160-Pin Quad Flatpacks

CACHE MEMORY FOR 80386DX

Abstract: 80386DX C9012 386DX 386DX bios 386DX motherboard 80387DX Cache Controller 80386DX 16 BIT
Contextual Info: AT40391B/392 Features • Two-Chip PC/AT Compatible Chip Set for 80386DX Systems Operating up to 40 MHz AT40391B System and Cache Controller AT40392 Data Buffer Controller Two 160-Pin Quad Flatpacks On-Chip Support for Direct-Mapped Write-Back Cache 0 Walt State Cache Read Hit and Programmable 0/1 Wait State

AT40391B25

Abstract: 80386DX 16 BIT AMI 8042 AT40391B-40
Contextual Info: AT40391B/392 Features • Two-Chip PC/AT Compatible Chip Set for 80386DX Systems Operating up to 40 MHz AT40391B System and Cache Controller AT40392 Data Buffer Controller Two 160-Pln Quad Flatpacks On-Chip Support for Direct-Mapped Write-Back Cache 0 Walt State Cache Read Hit and Programmable 0/1 Wait State

Contextual Info: AT40493/392 Features • Two-Chip PC/AT Compatible Chip Set for 80486 Based Systems Operating up to 50 MHz AT40493 System and Cache Controller AT40392 Data Buffer Controller Two 160-Pln Quad Flatpacks On-Chip Support for Direct-Mapped Write-Back Cache 0 Wait State Cache Read Hit and Programmable 0/1 Wait State

fast sram 200mhz 8k

Abstract: KS32C50100 ARM10TDMI block diagram ARM7 set associative ARM10TDMI ARM920T 1997 KS* I2C UART buffer ic KS32C5000A 196QFP
Contextual Info: Rev. 1.8 W - Network Business KS32C5000A 32-bit RISC Microcontroller for Networking Dec. 1998 Network Group , SYSTEM LSI ELECTRONICS December ‘98 Network Team CPU Roadmap KS32C5000A 1996 1997 1998 • 150 ~ 200MHz ARM9TDMI • 0.35/0.25um TLM • 1.0mA/MHz@2.5V

73d25

Abstract: at40206 peripheral controller
Contextual Info: AT40493/392 Features • • • • • • • • • • • • • • • • • • • Two-Chip PC/AT Compatible Chip Set for 80486 Based Systems Operating up to 50 MHz AT40493 System and Cache Controller AT40392 Data Buffer Controller Two 160-Pin Quad Flatpacks