16D 213 A O
Abstract: 16D 213 B H 16D 213 B A ic iq 6310a 16D 213 A R 6310A 16D 213 A L ALS6311A 74ALS6311A
Contextual Info: SN 74ALS6310A, SN ALS6311A STATIC COLUMN AND PAGE-MODE ACCESS DETECTORS D 3 0 2 0 , JUNE 1987 - REVISED DECEMBER 1989 Detects Present Row Equal to Last Row Address D W OR N P A C K A G E ITOP VIEW High-Performance Compare: ALS6310A CLK to HSA - 18 ns ALS6311A Address to HSA - 14 ns
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74ALS6310A,
74ALS6311A
ALS6310A
ALS6311A
SN74ALSG310A,
16D 213 A O
16D 213 B H
16D 213 B A
ic iq 6310a
16D 213 A R
6310A
16D 213 A L
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AN-615
Abstract: C1995 DP8420A DP8422A F245 tcpb9 20R4D
Contextual Info: National Semiconductor Application Note 615 Lawson H C Chang March 1989 INTRODUCTION This application note describes interfacing the DP8422A DRAM controller also applicable to DP8420A 21A to the 68000 (16 MHz) with slower memories This design is based upon burst mode access by holding RAS low and toggling
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DP8422A
DP8420A
DP8422A
20R4D)
ALS6311)
20-3A
AN-615
C1995
F245
tcpb9
20R4D
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schematic 80386
Abstract: e174 ALS6311 80386 microprocessor PAL20R4D AN619 DP8421A C1995 DP8420A DP8422A
Contextual Info: National Semiconductor Application Note 619 Lawson H C Chang February 1989 INTRODUCTION This application note describes how to interface the 80386 microprocessor to the DP8422A DRAM controller also applicable to DP8420A 21A with burst mode access The 80386 is running at 16 MHz 20 MHz or 25 MHz speed It is
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DP8422A
DP8420A
386PAL1
20-3A
schematic 80386
e174
ALS6311
80386 microprocessor
PAL20R4D
AN619
DP8421A
C1995
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ALS6311
Abstract: sn74als6311 6311m
Contextual Info: S N 74 A L S 6 3 10 , S N 74 A LS 6 3 11 S TATIC C O LU M N A N D PA G E-M O D E AC C ES S D ETEC TO R S TO P V IE W C LK C 1 U C LK E N C 2 High-Performance Compare: 'ALS6310 CLK to HSA - 18 ns
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D3020,
ALS6310
ALS6311
sn74als6311
6311m
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ALS6311
Abstract: 74S33 d0740
Contextual Info: TEXAS INSTR V la ± ^ X 1-U -CLOGICÏ TI y L | □ IDJI I L J u u n a o n i- g - r Ÿ S ~ ~ /~ 7 SN54ALS6310, ALS6311, SN74ALS6310, ALS6311 STATIC COLUMN AND PAGE-MODE ACCESS DETECTORS D 302 0, JU N E 1987 SN 54A LS' . . . J PACKAGE S N 74A LS' . . D W OR N PACKAGE
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SN54ALS6310,
SN54ALS6311,
SN74ALS6310,
SN74ALS6311
ALS6310
ALS6311
SN74ALSG31U,
74S33
d0740
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F245
Abstract: an6161 16L8D DP8422A an-6161 components combinational logic circuit AN61-61 AN-616 C1995 DP8420A
Contextual Info: National Semiconductor Application Note 616 Lawson H C Chang March 1989 INTRODUCTION This application note describes interfacing the DP8422A DRAM controller also applicable to DP8420A 21A to the 68020 with slower memories This design is based upon burst mode access by holding RAS low and toggling CAS It
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DP8422A
DP8420A
DP8422A
20-3A
F245
an6161
16L8D
an-6161
components combinational logic circuit
AN61-61
AN-616
C1995
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