DQD03 Search Results

t2d 68

Abstract: T2D 17 Line Interfaces "T2D"
Contextual Info: S3E D • ‘m i B b S DQD03bô H T H X E C _XECOM INC T -lS 'O l-^ ö XECOM XE0044/XE0044V Quad Phone Line Interfaces Description PIN CONFIGURATION The XE0044 and XE0044V provide four FCC compliant telephone line interfaces in a single compact package.

1P137

Abstract: IM37A INTEGRATED POWER SEMICONDUCTORS LTD LM337HVT LM337 LM337HVK LM337 TO-3 IP137A IP137AHV IP337AHV
Contextual Info: INTEGRATED POWER t>7 D E ^ 4 0250^0 00GQ3a4 S safe* 4825898 INTEG RATED 82D 0 0 3 0 4 POWER INTEGRATED 1.5A, 3-Terminal, Negative Adjustable Regulators , SEM IC O N D U C TO R S LTD. Features Description 1% initial voltage tolerance 0.01 %/V line regulation

8002 MOSFET

Abstract: FDA200 mosfet ac switch triac t24 parallel connection of MOSFETs series connection of mosfet FDA215 MOSFET driver
Contextual Info: CPClare MOSFET Driver CORPORATION OptoMOS Solid State MOSFET Driver DESCRIPTION CP Clare’s FDA MOSFET driver couples infrared light emitting diodes with a pair of proprietary photovoltaic integrated circuits. In addition to providing voltage for turn­

S20K460

Abstract: S20K550 s14k510 S14K550 s20k300 S20K275 so7K275 14DK390 VZC130 V250LA15A
Contextual Info: ONEIDA ELECTRONIC IFG INC 6792335 Sfl ONE IOA ELECTRONIC 58C MFG ï lE îJ L 7 T 2 3 3 S 000030b INC 00306 D #10 ONEIDA O-MOV OLA TYPE OZ95LA7A OZ95LA7B 0Z130LA10A OZ130LA10A 0Z150LA10A 0Z150LA10A 0Z250LA15A 0Z250LA2ÛA 0Z275LA15A 0Z275LA20A OZ320LA15A ÛZ320LA15A

16C650

Contextual Info: STARTECH ST16C650 An 2£* EX4RCompany Printed August 3, 1995 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFO’s AND INFRA­ RED ENCODER/DECODER PLCC Package DESCRIPTION 8 The ST16C650 is a universal asynchronous receiver and transmitter with 32 bytes transmit and receive

Contextual Info: White Electronic Designs W3E4128M4SxxBC ADVANCED* 2 Gb - 4x128Mx4, DDR SDRAM MCP FEATURES DESCRIPTION Bi-directional data strobe DQS The White Electronic Designs 2Gb DDR SDRAM is a synchronous dynamic random-acess memory supporting data transfer on each of the clock edges