DQ FLIP FLOP IC Search Results

74 HC 238 A

Contextual Info: 1 - * 4 /0 - 0 7 - 1 0 Technical D a ta . CD54/74HC174 CD54/74HCT174 File Number 1608 High-Speed CMOS Logic H A RR IS S E M I C O N D CP— [ > SECT OR 27E D 4 3 0 2 27 1 DG17b45 Dq - -Q o Hex D-Type Flip-Flop with Reset 01- -°1 Positive-Edge Triggered d2-

4076B

Abstract: 74C173
Contextual Info: 4076B/74C173/54C173 QUAD D FLIP-FLOP WITH 3-STATE OUTPUT D E S C R IP T IO N — T h e 4 0 7 6 B is a Q uad E dge-Triggered D F lip -F lo p w ith fo u r Data Inputs {DQ-D3 , tw o active LO W Data Enable Inputs ED g -ED ^ ), an edge-trigge red C lo ck In p ut (C P ), fo u r 3-State O u t­

SC10000

Abstract: diode AN2A
Contextual Info: TEKTRONIX INC/ TRI ÖUINT 2bE T> EU Ô^GbSlfl 0000b3û 0 Q T R ü " P 4 2 - U - 0 » ïM û i G ig a B it L o g ic SC10Q00 GaAs Standard Cell Array S C 1 0 0 0 0 D E S C R IP T IO N T h e S C 1 0 0 0 0 S tandard Cell Array is ideal for the developm ent of low power, high perform ance V LS I

Contextual Info: 33 December 1996 CD74FCT377T Fast CMOS Octal D Flip-Flop with Clock Enable Features Description • Advanced 0.8 micron CMOS Technology T he C D 7 4 F C T 3 7 7 T is an 8-b it w id e octal d e sig ned w ith e ig h t ed g e -trig g e re d D -type flip -flop s w ith individual D inputs

stc 8080A+упътване

Contextual Info: 8080A/8080A-1/8080A-2 8-BIT N-CHANNEL MICROPROCESSOR • TTL Drive Capability ■ 2 jus -1:1.3 jus, -2:1.5 jas Instruction Cycle ■ Powerful Problem Solving Instruction Set ■ Decimal, Binary, and Double Precision Arithmetic ■ Ability to Provide Priority Vectored

Contextual Info: 7 * t M54/74HC373 M54/74HC533 SGS-THOMSON ItLG OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC373 NON INVERTING - HC533 INVERTING • HIGH SPEED tpD = 11 ns TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Icc = 4 nA (MAX.) AT Ta = 25 °C ■ HIGH NOISE IMMUNITY V nih = Vnil = 28 % Vcc (MIN.)

vhdl code for TRAFFIC LIGHT CONTROLLER SINGLE WAY

Abstract: traffic light controller vhdl coding vhdl code for TRAFFIC LIGHT CONTROLLER 4 WAY VHDL code for traffic light controller traffic light using VHDL vhdl code for TRAFFIC LIGHT CONTROLLER new traffic light controller vhdl design counter traffic light Code vhdl traffic light schematic counter traffic light
Contextual Info: APPLICATION NOTE  XAPP 105 January12, 1998 Version 1.0 A CPLD VHDL Introduction 4* Application Note Summary This introduction covers the basics of VHDL as applied to Complex Programmable Logic Devices. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language

HC574

Contextual Info: *57 SGS-THOMSON ILiOTOiOOS M54/74HC564 M54/74HC574 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC564 INVERTING - HC574 NON INVERTING • HIGHSPEED f M A X = 62 MHz TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 4 (MAX.) AT T a = 25 °C . HIGH NOISE IMMUNITY

8080A

Abstract: intel 8080a intel 8080 stc 8080A+упътване
Contextual Info: 8080A/8080A-1 /8080A-2 8-BIT N-CHANNEL MICROPROCESSOR • TTL Drive Capability ■ 2 ¡is -1 :1 .3 Cycle /a s , -2:1.5 /a s Instruction ■ Powerful Problem Solving Instruction Set ■ Decimal, Binary, and Double Precision Arithmetic ■ Ability to Provide Priority Vectored

74ls76 jk flip-flop logic symbol and truth table

Abstract: 7476PC 7476 PIN DIAGRAM 7476 truth table 74LS76PC 74LS76 dual flip-flop pin diagram of 7476 74LS76D 74LS76DC Jk 74ls76 pin out
Contextual Info: 76 CONNECTIO N DIAGRAM PINOUT A ^54/7476 OZZô/b> ^54H /74H 76 G f / c t l l/54LS/74LS76 DUAL JK FLIP-FLOP With Separate Sets, Clears and Clocks c p i [T DESCRIPTION — The ’76 and 'H76 are dual JK m aster/slave flip -flo p s with separate Direct Set, D irect Clear and Clock Pulse inputs fo r each flip -flop .

micron ddr3

Abstract: DDR3 timing diagram DDR3 model verilog codes Verilog DDR3 memory model micron memory model for ddr3 MT41J128M8 Verilog DDR memory model DDR3 "application note" DDR3 DQ flip flop IC
Contextual Info: Maxim > Design Support > App Notes > T/E Carrier and Packetized > APP 5120 Keywords: DDR1, DDR3, jitter, buffer, TDMoP, TDM over packet, DDR, SDRAM, PDV, PSN, double data rate APPLICATION NOTE 5120 Aug 26, 2011 Using a DDR3 Memory Module with the DS34S132

intel 8080A instruction set

Abstract: stc 8080A 8080A-1 intel 8080a 1117cz stc 8080A+
Contextual Info: intei 8080A/8080A-1 /8080A-2 8-BIT N-CHANNEL MICROPROCESSOR TTL Drive Capability Decimal, Binary, and Double Precision A rithm etic 2 ¡Xs —1:1.3 u s , —2:1.5 fis Instruction Cycle Ability to Provide Priority V ectored Interrupts Powerful Problem Solving Instruction

transistor E111

Contextual Info: b & r J> MOTOROLA SEMICONDUCTOR m MOTOROLA TECHNICAL DATA b3b72S2 DDTMTTb <141 « M O T H SC L O G I C 1 MC10E211 M C100E211 1:6 Differential Clock Distribution Chip The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The device can be

Contextual Info: SY10E131 SYNERG Y 4-BIT D FLIP-FLOP OTlUltlJl SEMICONDUCTOR DESCRIPTION FEATURES • 1100 MHz min. toggle frequency. The SY10E/100E/101E131 is a high speed quad master-slave D-type flip- flop with differential outputs designed for use in new high performance ECL systems. The flip-flops may be individually

1117cz

Abstract: stc 8080 8080a intel microprocessor pin diagram AFN-00735B 8080a stc 8080 h intel 8080a memory110 intel 8080A instruction set 8080A CPU
Contextual Info: 8080A/8080A-1/8080A-2 8-BIT N CHANNEL MICROPROCESSOR • TTL Drive Capability ■ 16-Bit Stack Pointer and Stack Manipulation instructions for Rapid Switching of the Program Environment ■ 2 us —1:1.3 ptS, -2 :1 .5 jus Instruction Cycle ■ Powerful Problem Solving Instruction

LM 3771

Abstract: interfacing STEPPER MOTOR with z80 microprocessor pbl 3771 d2
Contextual Info: ERICSSON ^ May 1998 P BM 3960 Microstepping Controller/ Dual D i g i t a l - t o - A n a l o g C o n v e r t e r Description Key Features PBM 3960 is a dual 7-bit+sign, Digital-to-Analog Converter DAC especially developed to be used together with the PBL 3771, Precision Stepper Motor driver in

transistor E111

Contextual Info: MC10E211, MC100E211 5V ECL 1:6 Differential Clock Distribution Chip The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The E211 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed

Contextual Info: HY5216256 Series -HYUNDAI 256Kx 16-bit Video RAM with 2CAS Introduction Overview The 4megabit Video RAM is an application specific memory device designed for graphics applications. It comprises a 256k x16 DRAM memory array interfaced to a 256 x16 Serial Access Memory SAM , or register.

Contextual Info: TC74HCT373AP/AF/AFW TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT373AP,TC74HCT373AF,TC74HCT373AFW Octal D-Type Latch with 3-State Output The TC74HCT373A is a high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS

Contextual Info: •HYUNDAI H Y 5 2 1 6 2 5 7 256K x S e r ie s 16-bit Video RAM with 2WE Introduction Overview The 4megabit Video RAM is an application specific memory device designed for graphics applications. It comprises a 256k x16 DRAM memory array interfaced to a 256 x16 Serial Access Memory SAM , or register.

TGT2-0032-30-24

Abstract: TGT2-0032-30-24/TOPS1KX
Contextual Info: Freescale Semiconductor Application Note Document Number:AN4537 Rev. 1, 10/2012 3-Phase PMSM Vector Control Using the PXS20 and Tower System by: Libor Prokop and Marek Stulrajter Roznov pod Radhostem Czech Republic Contents 1 Introduction 1

ic el 434

Abstract: MSM5299A MSM6255 QFP100-P-1420-K QFP100-P-1420-V1K
Contextual Info: O K I Sem icon d u cto r M SM 5299A 8O-DOT SEGMENT DRIVER G EN ER A L D ESCR IPTIO N T he M SM 5299A is a dot m atrix LC D segm ent d river LSI w hich is fabricated b y C M O S low pow er m etal gate technology. T his LSI con sists o f an 80-bit bid irectional shift register, 80-bit latch, 80b it level shifter and 80-bit 4-lev el driver.

74S174

Abstract: 74S175 SN54S174J SN54S174X SN74S174J SN74S174N SN74S174X SN74S175J
Contextual Info: Am54S/74S174 •Am54S/74S175 Hex/Quadruple D-Type Flip Flops With Clear Distinctive Characteristics • Positive edge-triggered D flip -flop s • 4-B it and 6-B it high-speed parallel registers. • Common clock and com m on clear. • 100% re lia b ility assurance testing in com pliance w ith

Contextual Info: v TC74HCT373AP/AF/AFW v TC74HCT533AP/AF OCTAL D - T Y P E LATCH WITH 3 -S T A T E OUTPUT TC74HCT373AP/AF/AFW N O N -IN VERTING TC74HCT533AP/A F/AFW INVERTING The TC74HCT373A and HCT533A are high speed C M O S O C T A L L A T C H with 3 - S T A T E O U T P U T fabricated with