DIGITAL CLOCK DESIGN Search Results

ICS421-05

Abstract: CCD camera board CCD MARKING
Contextual Info: DATASHEET ICS421-05 DIGITAL VIDEO CAMERA CLOCK Description Features The ICS421-05 is a low-power, low-jitter clock synthesizer developed for digital camera applications. The device accepts a 27 MHz input clock to support common digital video camera interface frequencies

AN1405

Abstract: AN1406 digital clock design PECL Motorola
Contextual Info: Low Jitter, Low Emission Timing Solutions For High Speed Digital Systems A Design Methodology The Challenges of High Speed Digital Clock Design Designing clock generation and distribution systems for today’s high speed digital electronic devices poses numerous challenges to the design

CLK180

Abstract: DS485 vhdl code for DCM
Contextual Info: Digital Clock Manager DCM Module DS485 April 24, 2009 Product Specification Introduction LogiCORE Facts The Digital Clock Manager (DCM) primitive in Xilinx FPGA parts is used to implement delay locked loop, digital frequency synthesizer, digital phase shifter, or a

Contextual Info: Rev 2; 9/08 I2C Digital Input RTC with Alarm Features The DS1375 digital real-time clock RTC is a low-power clock/calendar that does not require a crystal. The device operates from a digital clock input pin at one of four frequencies: 32.768kHz, 8.192kHz, 60Hz, or 50Hz.

DS1375

Abstract: J-STD-020A 8192Hz 12 Hour Digital Clock Circuit
Contextual Info: Rev 0; 4/03 2-Wire Digital Input RTC with Alarm Features The DS1375 digital real-time clock RTC is a low-power clock/calendar that does not require a crystal. The device operates from a digital clock input pin at one of four frequencies: 32.768kHz, 8.192kHz, 60Hz, or 50Hz.

Contextual Info: •J» GOULD T1 /CEPT Digital Trunk PLL Electronics Preliminary Data Sheet COMMUNI­ CATION S8940 Digital Trunk Transmission Links • ST-BUS Clock and Frame Pulse source Features • Provides T1 clock at 1.544 MHz locked to input frame pulse • Sources CEPT 30 + 2 Digital Trunk/ST-BUS clock

phase detector in RTL

Abstract: ADPLL phase detector CH-2555 ADPLL with low jitter
Contextual Info: iniADPLL All Digital Phase Locked Loop Features • • • • • • • • • General Description The iniADPLL is an all digital implementation of a phase locked loop. PLLs are widely used in telecom applications for clock recovery, clock generation and clock supervision. The all digital solution needs no external

home electronic projects schematic

Abstract: CLC011EB
Contextual Info: CLC011 Serial Digital Video Decoder General Description National’s Comlinear CLC011, Serial Digital Video Decoder, decodes and descrambles SMPTE 259M standard Serial Digital Video datastreams with serial clock into 10-bit parallel words and a corresponding word-rate clock. SMPTE 259M

CLC011

Abstract: CLC011ACQ CLC014 CLC016
Contextual Info: CLC011 Serial Digital Video Decoder General Description National’s Comlinear CLC011, Serial Digital Video Decoder, decodes and descrambles SMPTE 259M standard Serial Digital Video datastreams with serial clock into 10-bit parallel words and a corresponding word-rate clock. SMPTE 259M

CLC011

Abstract: CLC011ACQ CLC014 CLC016
Contextual Info: CLC011 Serial Digital Video Decoder General Description National’s Comlinear CLC011, Serial Digital Video Decoder, decodes and descrambles SMPTE 259M standard Serial Digital Video datastreams with serial clock into 10-bit parallel words and a corresponding word-rate clock. SMPTE 259M

Contextual Info: High-performance Clock Generator Series 3ch Clock Generators for Digital Cameras BU2394KN,BU2396KN No.09005EAT02 ●Description These clock generators are an IC generating three types of clocks – CCD, USB, and VIDEO clocks – necessary for digital still camera systems and digital video camera systems, with a single chip through making use of the PLL technology.

x1 capacitor

Contextual Info: DATASHEET IDT5V50009 SPREAD SPECTRUM CLOCK GENERATOR Description Features The IDT5V50009 generates a low EMI output clock and a reference clock from a clock or crystal input. The part is designed to lower EMI through the application of spreading a clock. Using IDT’s proprietary mix of analog and digital

YM3434

Abstract: YM3433B YM3433 ym34 YM3433B-D YM3433B-F Yamaha oversampling filter yamaha LSI 24pin yamaha 40
Contextual Info: YAMAHALSI Y M 3433B ALCDF 2 channel 8 times oversampling Digital Filter Operatable at system clock independent from input serial clock. • OUTLINE The digital filter’s own system clock rate must be considerably faster than the input bit clock rate and at the same time synchronism is required in the system as a whole. Thus

MK17268L

Abstract: CY25819 MK1726-08
Contextual Info: DATASHEET MK1726-08 SPREAD SPECTRUM CLOCK GENERATOR Description Features The MK1726-08 generates a low EMI output clock and a reference clock from a clock or crystal input. The part is designed to lower EMI through the application of spreading a clock. Using IDT’ proprietary mix of analog and digital

HC135

Contextual Info: RFM HC1351 • Quartz Frequency Stability • Excellent Jitter and Symmetry Performance • Rugged, Hermetic Metal DIP Case 625.0 MHz Digital Clock The HC1351 digital clock is designed for use with high speed CPUs operating at 125,156.25 or 208.333 MHz. The 625 MHz fundamental oscillation mode, made

IDT5V50013

Contextual Info: DATASHEET IDT5V50013 LOW EMI CLOCK GENERATOR Description Features The IDT5V50013 generates a low EMI output clock from a clock input. The part is designed to dither the LCD interface clock for PDAs, printers, scanners, modems, copiers, and others. Using IDT’s proprietary mix of analog and digital

Contextual Info: SM320DM6446 Digital Media System-on-Chip www.ti.com SPRS607A – JUNE 2009 – REVISED JUNE 2009 1 Digital Media System-on-Chip DMSoC 1.1 Features • • • • High-Performance Digital Media SoC – 594-MHz C64x+ Clock Rates – 297-MHz ARM926EJ-S™ Clock Rates

Contextual Info: SM320DM6446 Digital Media System-on-Chip www.ti.com SPRS607A – JUNE 2009 – REVISED JUNE 2009 1 Digital Media System-on-Chip DMSoC 1.1 Features • • • • High-Performance Digital Media SoC – 594-MHz C64x+ Clock Rates – 297-MHz ARM926EJ-S™ Clock Rates

Universal electronics tv remote control circuit

Abstract: TMS320DM6446
Contextual Info: SM320DM6446 Digital Media System-on-Chip www.ti.com SPRS607A – JUNE 2009 – REVISED JUNE 2009 1 Digital Media System-on-Chip DMSoC 1.1 Features • • • • High-Performance Digital Media SoC – 594-MHz C64x+ Clock Rates – 297-MHz ARM926EJ-S™ Clock Rates

IMX 145

Contextual Info: SM320DM6446 Digital Media System-on-Chip www.ti.com SPRS607A – JUNE 2009 – REVISED JUNE 2009 1 Digital Media System-on-Chip DMSoC 1.1 Features • • • • High-Performance Digital Media SoC – 594-MHz C64x+ Clock Rates – 297-MHz ARM926EJ-S™ Clock Rates

rfid timer0

Abstract: pal 007c tk 1838 074c 1A60 tms 4464 8038 ic tester circuit diagram arm 2510 n td 1410 nt 407f
Contextual Info: TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282F – DECEMBER 2005 – REVISED MARCH 2008 1 Digital Media System-on-Chip DMSoC 1.1 Features • • • • High-Performance Digital Media SoC – 594-MHz C64x+ Clock Rate – 297-MHz ARM926EJ-S™ Clock Rate

Basic ARM9 block diagram

Contextual Info: TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282F – DECEMBER 2005 – REVISED MARCH 2008 1 Digital Media System-on-Chip DMSoC 1.1 Features • • • • High-Performance Digital Media SoC – 594-MHz C64x+ Clock Rate – 297-MHz ARM926EJ-S™ Clock Rate

LM8562

Abstract: lm8560
Contextual Info: Ordering number: EN 2658A PMOS LSI LM8562 Digital Alarm Clock Overview Package Dimensions The LM8562 is a digital clock-use LSI having features such as easy setting, two alarms. Since the LM8562 is designed to be able to direct drive an LED panel of duplex type, the package

HC135

Abstract: DIP14S-8
Contextual Info: HC1358 • Quartz Frequency Stability • Excellent Jitter and Sym m etry Performance • Rugged, Hermetic M etal DIP Case 650.0 MHz Digital Clock The HC1358 digital clock is designed for use with high speed CPUs operating at 130,162.5 or 216.6667 MHz. The 650 MHz fundamental oscillation mode, made