DID A2 198 Search Results

Contextual Info: AS7C3256 3.3V 32Kx8 CMOS SRAM Features • Organization: 32,768 words x 8 bits • Single 3.3 ± 0.3V power supply • High speed - 1 0 /1 2 /1 5 /2 0 ns address access time - 3 / 3 / 4 / 5 ns output enable access time • Very low power consumption - Active: 198 mW max, 12 ns cycle

Contextual Info: AS7C3256 3.3V 32Kx8 CMOS SRAM 1O rganization: 3 2 ,7 6 8 w ords x 8 bits 1Single 3.3 ± 0.3V pow er supply 1H igh speed - 1 2 /1 5 /2 0 ns address access tim e - 3 / 4 / 5 ns output enable access tim e 1Very low pow er consum ption - Active: 198 m W max, 12 ns cycle

6A14

Abstract: TSOP8
Contextual Info: Features • Organization: 32,768 words x 8 bits • Single 3.3 ± 0.3V power supply • High speed - 12 / 1 5 /2 0 ns address access time - 3 /4 /5 ns output enable access time • Very low power consumption - Active: 198 mW max, 12 ns cycle - Standby: 3.6 mW max, CMOS I/O

Contextual Info: AS7C3256 3.1V 32Kx8 CMOS SRAM Features •O iganization: 32,7 68 w o ris x 8 b i s • Singie 3 3 ± 0 3V pow e r sappiy • H igh qpesd - 1 2 / 1 5 / 2 0 nsaddiess access tin e - 3 / 4 / 5 ns output enable access tin e •Veiy low pow e r consjm ption -Active: 198 mW max, 12 ns cycle

Contextual Info: H igh Perform ance lMx4 CMOS DRAM |B AS4C14405 A ! M x 4 CMOS EDO DRAM Preliminary information Features • O r g a n iz a t io n : 1 , 0 4 8 , 5 7 6 w o r d s x 4 b its • 1 0 2 4 r e f r e s h c y c le s , 1 6 m s r e f r e s h in t e r v a l • H ig h sp e ed

Contextual Info: H ig h P e rfo rm a n c e lMx4 CMOS DRAM A S4C 14400 h II , 1 1M x 4 CMOS DRAM fast page m ode Prelim inary inform ation Features • 1 0 2 4 r e f r e s h c y c le s , 1 6 m s r e f r e s h in te r v a l • O r g a n iz a t io n : 1 , 0 4 8 ,5 7 6 w o r d s x 4 b its

Contextual Info: AS7C3256 3.3V 32Kx8 CMOS SRAM Features • Easy memory expansion with CE and OE inputs • TTL-compatible, three-state I/O • Ideal for cache, modem, portable computing - 75% power reduction during CPU idle mode • 28-pin JEDEC standard packages - 300 mil PDIP commercial

did a2 198

Abstract: AS7C3256-15PC
Contextual Info: AS7C3256 3.3V 32Kx8 CMOS SRAM Features • Easy memory expansion with CE and OE inputs • TTL-compatible, three-state I/O • Ideal for cache, modem, portable computing - 75% power reduction during CPU idle mode • 28-pin JEDEC standard packages - 300 mil PDIP commercial

GC80303 SL57T

Abstract: SL57T GC80303 gc80302 intel DOC intel 386 user manual X3310 272353
Contextual Info: Intel 80303 and 80302 I/O Processors Specification Update November 15, 2001 Notice: The Intel® 80303 and Intel® 80302 I/O Processors processor may contain design defects or errors known as errata. Characterized errata that may cause the product’s behavior to deviate

Contextual Info: H igh P erfo rm a n ce •■ A S 7 C 1024 H 128Kx8 CMOS SRAM A S7C 31024 1 2 8 K X 8 C M O S SRAM C o m m o n I / O • O r g a n iz a tio n : 1 3 1 ,0 7 2 w o r d s x 8 b its • T T L /L V T T L -c o m p a tib le , th r e e - s ta te I / O • H ig h sp ee d

GC80303

Abstract: GC80303 SL57T GC80302 intel 80302 SL57T intel DOC 272353
Contextual Info: Intel 80303 and 80302 I/O Processors Specification Update May 6, 2003 Notice: The Intel® 80303 and Intel® 80302 I/O Processors processor may contain design defects or errors known as errata. Characterized errata that may cause the product’s behavior to deviate

land pattern for TSOP 2 44 PIN

Abstract: land pattern for TSOP 2 54 pin land pattern for TSOP 56 pin psop 44 land pattern PQFP 208
Contextual Info: High perform ance 512KX32 CMOS SGRAM 16 Megabit CMOS synchronous graphic RAM Advance information • Organization - 131,072 words x 32 bits x 4 banks • Fully synchronous - All signals referenced to positive edge of dock • Four internal banks controlled by BA0/BA1 bank select

GC80303 SL57T

Abstract: GC80303 GC80302 of bc 237 b sl57t intel 80302 CELERON D 331 NFP-32 273355 Q229 celeron
Contextual Info: Intel 80303 and 80302 I/O Processors Specification Update March 2007 The Intel® 80303 and 80302 I/O Processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available

Contextual Info: CY7C67300 EZ-Host Programmable Embedded USB Host/Peripheral Controller with Automotive AEC Grade Support Cypress Semiconductor Corporation Document #: 38-08015 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 7, 2006

land pattern for TSOP 2 54 pin

Abstract: TSOP 54 land pattern AS7C1024 AS7C31024 land pattern for TSOP 2 44 PIN
Contextual Info: H igh P erfo rm an ce •■ 128Kx8 A S7C 1024 A S7C 31024 H CMOS SRAM 1 2 8 K X 8 CM O S SRAM C o m m o n I / O Features • O rg a n iz a tio n : 1 3 1 ,0 7 2 w o rd s x 8 b its • H ig h sp e ed - 3 0 0 m il PDIP a n d SOJ - 1 0 / 1 2 / 1 5 / 2 0 n s ad d ress access tim e

Contextual Info: II High p e rfo rm an c e 6 4 K x 52 » A S7CÌ643 2 CM O S SRAM A 6 4 K x 3 2 Synchronous burst S R A M Features • F low -th rou gh op tion • Fast clo ckin g sp e ed : 1 0 0 / 8 3 / 6 6 M H z • Fast clock to d ata access: 5 / 6 / 7 ns • Self-tim ed w rite cycle

f7319

Abstract: F0413 DMS-100 provisioning tables F1814 AD152 mbgs F0411 F1831 f1815 AG110
Contextual Info: Multilocation Business Groups Multilocation Business Group MBG technology provides a new way of connecting MDC locations—and a new source of revenue for local carriers Multilocation Business Group (MBG) services are designed to meet the needs of organizations

land pattern for TSOP 2 54 pin

Abstract: land pattern for TSOP 56 pin TSOP 54 land pattern 40013A land pattern for TSOP
Contextual Info: n H igh p e rfo rm a n c e 1 M X 8 /5 1 2 K X 1 6 2.2V CMOS Flash EEPROM AS29LL8ÜÖ II 1 M X 8 / 5 1 2 K X 1 6 CMOS Flash EPROM Advance information Features •O rganization: 1M x 8/512K x 16 • Sector architecture - • Low power consumption - 8 mA typical read current

KJE T3

Abstract: 256X128X8 AS7C3256
Contextual Info: A S7C 3256 A 3.3V 3 2 K x 8 C M O S SRAM O rg an izatio n : 3 2 ,7 6 8 w o rd s X 8 bits Single 3 .3 ± 0.3V p o w e r su p p ly H ig h speed - 1 2 / 1 5 / 2 0 ns ad d ress access tim e - 3 / 4 / 5 ns o u tp u t en ab le access tim e V ery lo w p o w e r c o n su m p tio n

r100kohm

Abstract: lfxtal r47kohm CTM8B56EN
Contextual Info: CTM8B54E/55E/56E/57E EPROM-Based 8-Bit CMOS Microcontroller FEATURES • Total of 33 single word instructions . • The fast execution time may be 200ns for all single cycle instructions under 20MHz operating. • Operating voltage range: 2.3V ~ 6.5V • 8-bit data bus.

Contextual Info: H ig h P e r f o r m a n c e 3 2 K x 8 3 .3 V C M O S SR AM a i A S7C 3256 A Low voltage 3 2K X 8 CMOS SRAM • T T L -co m p atib le, th re e -s ta te I / O • S ingle 3 .3 ± 0 .3 V p o w e r s u p p ly • Id eal f o r cache, m o d e m , p o rta b le c o m p u tin g

MTU8B56EP

Abstract: lfxtal MTU8B56E 101P MTU8B54E MTU8B55E MTU8B57E xtal 12MHz 97975 Myson Technology
Contextual Info: MYSON TECHNOLOGY MTU8B54E/55E/56E/57E EPROM-Based 8-Bit CMOS Microcontroller FEATURES • Total of 33 single word instructions . • The fast execution time may be 200ns for all single cycle instructions under 20MHz operating. • Operating voltage range: 2.3V ~ 6.5V

VLN 2003

Abstract: AS7C1025 AS7C31025 20013A ldh 0470
Contextual Info: A S7C1025 AS7C31025 5V/3.3V 128K •8 C M O S SRAM iCom nion I/O Features • Organization: 131,072 w ords X 8 bits • High speed - 1 0 / 1 2 /1 5 / 2 0 ns address access time - 3 / 3 / 4 / 5 ns output enable access time • Low pow er consum ption - Active:

pic18 an953

Abstract: 4558 dd 97120 lfsr galois prbs using lfsr 811b fc 4558 DS00821 f 4558 MOV1
Contextual Info: AN953 Data Encryption Routines for the PIC18 Author: David Flowers Microchip Technology Inc. INTRODUCTION This Application Note covers four encryption algorithms: AES, XTEA, SKIPJACK and a simple encryption algorithm using a pseudo-random binary sequence generator. The science of cryptography