DEMULTIPLEXERS Search Results

54HC154

Contextual Info: SN54HC154, SN74HC154 LINE TO 16 LINE DECODERS/DEMULTIPLEXERS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 • Decodes 4 Binary-Coded Inputs into One of 16 Mutually Exclusive Outputs • Performs the Demultiplexing Function by Distributing Data From One Input to Any

Contextual Info: UT54ACS 139/UT54ACTS 139 Radiation-Hardened Dual 2-Line to 4-Line Decoders/Demultiplexers PINOUTS FEATURES 16-Pin DIP Top View • Incorporates two enable inputs to simplify cascading and/or data reception • 1.2 1 radiation-hardened CMOS - Latchup immune

051b

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B - MARCH 1987 - REVISED JULY 1996 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems SN54F13 8 . . . J PACKAGE SN74F138. . . D OR N PACKAGE TOP VIEW u Incorporates Three Enable Inputs to

Contextual Info: SN74ALS137, SN74AS137, SN54ALS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D2661, APRIL 1982 - REVISED M AY 1986 Combings Decoder and 3-Bit Addreis Latch SN54ALS137 . . . J PACKAGE SN74ALS137, SN74AS137 . . . D O R N PACKAGE Incorporates 2 Output Enables to Simplify

LS138

Abstract: SN54ALS138
Contextual Info: TYPES SN54ALS138, SN54AS138, SN74ALS138, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D 2 6 6 1 , APRIL 1 9 8 2 — REVISED DECEMBER 1 9 8 3 Designed Specifically for High-Speed Mem ory Decoders and Data Transmission Systems SN 54A LS138, SN 54A S 138 .

SN74F138

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051 A - D2932, MARCH 1987 - REVISED OCTOBER 1993 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception

cd4051a

Abstract: TP4053 TP4051 TP4052 TRTE CD4052A KSL 2101
Contextual Info: f TYPES TF4051A, TF4052A, TF4053A. TP4051A, TP4052A, TP4053A ANALOG MULTIPLEXERS/DEMULTIPLEXERS I CMOS LOGIC CIRCU ITS S E P 7 fc M « L H 1 9 7 ‘j Desired to be Interchangeable with RCA CD4051A, CD4052A, and CD4053A Difference in ron Between Switches in One Package Typically 5 12 at

SN54ALS137

Contextual Info: SN74ALS137, SN74AS137, SN54ALS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D2661, APRIL 1982 - REVISED MAY 1986 Combines Decoder and 3-Bit Address Latch Incorporates 2 Output Enables to Simplify Cascading SN54ALS137 . . . J PACKAGE SN74ALS137, SN74AS137 . . . D OR N PACKAGE

Contextual Info: SN54LV138, SN74LV138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SC LS190P- FEBRUARY 19 9 3 - REVISED JULY 1996 EPIC Enhanced-Performance Implanted CMOS 2-fi Process Typical Vqlp (Output Ground Bounce) < 0.8 V at Vc c , Ta = 25°C SN54LV138. . . J OR W PACKAGE

74HC239

Abstract: C-239 SN74HC239
Contextual Info: SN54HC239, SN74HC239 DUAL 2-LINE TO 4 LINE DECODERS/DEMULTIPLEXERS D 2 8 0 4 . MARCH 1 9 8 4 -R E V IS E D SEPTEMBER 1987 • • S N 5 4 H C 2 3 9 . . . J P AC KAG E S N 7 4 H C 2 3 9 . . . D W OR N P A C K A G E TO P V IE W ! IG C 1 U 1A C 2 Incorporates 2 Enable Inputs to Simplify

Contextual Info: SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS S CLS258C - DECEM BER 1995 - REVISED JULY 1996 Operating Range 2-V to 5.5-V Vqc E P IC * Enhanced-Performance Implanted CMOS Process SN54AMC138 . . . J O R W PACKAGE SN74AHC138 . . . D, DB, N, OR PW PACKAGE

Contextual Info: SN54HC139, SN74HC139 DUAL 2 LINE TO 4-LINE DECODERS/DEMULTIPLEXERS D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 D esigned S pecifically for H igh-Speed S N 5 4 H C 1 3 9 . . . J PACKAGE S N 7 4 H C 1 3 9 . . . O W OR N PACKAGE M e m o ry D ecoders and D ata Transm ission

Contextual Info: SN54HCT237, SN74HCT237 3 LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES D 2 8 0 4 , M A R C H 1 9 8 4 - R E V I S E D JU N E 1 9 8 9 • Inputs are TTL-Voltage Compatible S N 5 4 H C T2 3 7 . . . J PA C KA G E SN 74H C T237 . . . N PACKAG E •

Contextual Info: SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDAS055E – APRIL 1982 – REVISED JULY 1996 D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify

sn74als138a ti

Abstract: SN54ALS138
Contextual Info: SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDAS055E – APRIL 1982 – REVISED JULY 1996 D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify

Contextual Info: SN54ALS139, SN74ALS139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SDAS204A – APRIL 1982 – REVISED DECEMBER 1994 • • • SN54ALS139 . . . J PACKAGE SN74ALS139 . . . D OR N PACKAGE TOP VIEW Designed Specifically for High-Speed Memory Decoders and Data Transmission

Contextual Info: SN54LV4051A, SN74LV4051A 8-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS428B – MAY 1999 – REVISED JUNE 2000 D D D D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on

Contextual Info: SN54HCT138, SN74HCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS171C – MARCH 1984 – REVISED MAY 1997 D SN54HCT138 . . . J OR W PACKAGE SN74HCT138 . . . D, N, OR PW PACKAGE TOP VIEW A B C G2A G2B G1 Y7 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC

Contextual Info: SN54LV4051A, SN74LV4051A 8-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS428B – MAY 1999 – REVISED JUNE 2000 D D D D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on

Contextual Info: SN54LV138A, SN74LV138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS395C – APRIL 1998 – REVISED MAY 2000 D D D D D D description The ’LV138A devices are 3-line to 8-line decoders/demultiplexers designed for 2-V to 5.5-V VCC operation. SN54LV138A . . . J OR W PACKAGE

19ba

Contextual Info: 54AC11238, 74AC11238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D3103. APRIL 1988 - REVISED APRIL 1993 * * * * * * * * Designed Specifically for High-Speed Memory Decoders and Data Transmission

74HC239

Abstract: C-239
Contextual Info: SN 54H C 239, SN74H C239 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS 0 2 8 0 4 , M A R C H 1 9 8 4 -R E V IS E D JUNE 1 9 8 9 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems SN 64H C239 . . . J PACKAG E S N 7 4 H C 2 3 9 . . 0 * OR N P A C K A G E

lw051a

Abstract: LV4051 LW051
Contextual Info: SN54LV4051A, SN74LV4051A 8-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS SCLS428H − MAY 1999 − REVISED APRIL 2005 Y4 Y6 COM Y7 Y5 INH GND GND 15 3 14 4 13 5 12 6 11 7 10 8 9 Y6 COM Y7 Y5 INH GND VCC Y2 Y1 Y0 Y3 A B C 1 16 2 15 3 14 Y2 Y1 13 Y0 12 Y3 11 A

HA139

Contextual Info: SN54AHC139, SN74AHC139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS259K − DECEMBER 1995 − REVISED MARCH 2003 D Memory Decoders and Data-Transmission Systems Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception SN54AHC139 . . . J OR W PACKAGE