DDU12H Search Results

DDU12H

Abstract: DDU12H-10 DDU12H-100 DDU12H-20 DDU12H-25 DDU12H-40 DDU12H-50 DDU12H-75 t10 9 smd
Contextual Info: DDU12H data 3 delay devices, inc. 5-TAP, ECL-INTERFACED FIXED DELAY LINE SERIES DDU12H FEATURES PACKAGES GND • • •  Ten equally spaced outputs Fits in 300 mil 32-pin DIP socket Input & outputs fully 10KH-ECL interfaced & buffered 1 32 GND 31 T1

DDU12H

Contextual Info: DDU12H data 3 delay devices, inc. 5-TAP, ECL-INTERFACED FIXED DELAY LINE SERIES DDU12H FEATURES PACKAGES GND • • •  Ten equally spaced outputs Fits in 300 mil 32-pin DIP socket Input & outputs fully 10KH-ECL interfaced & buffered 1 32 GND 31 T1

t8 smd transistor

Abstract: DDU12H DDU12H-10 DDU12H-100 DDU12H-20 DDU12H-25 DDU12H-40 DDU12H-50 DDU12H-75 t10 9 smd
Contextual Info: DDU12H data 3  delay devices, inc. 5-TAP, ECL-INTERFACED FIXED DELAY LINE SERIES DDU12H FEATURES PACKAGES GND • • • Ten equally spaced outputs Fits in 300 mil 32-pin DIP socket Input & outputs fully 10KH-ECL interfaced & buffered GND T1 1 32 T2

1T813

Abstract: SMD hi4
Contextual Info: DDU12H data delay devices,vinc 5-TAP, ECL-INTERFACED FIXED DELAY LINE SERIES DDU12H FEATURES PACKAGES GND C 1 W 32 □ • • • Ten equally spaced outputs Fits in 300 mil 32-pin DIP socket Input & outputs fully 10KH-ECL interfaced & buffered GND 31 □

Contextual Info: data W3V/ delay W devices/inc. Digital Delay Units SERIES DDU-12H 10 Taps ECL Interfaced Test Conditions: inp u t p u ls e -w id th : 1 5 0 % o f to tal d elay. In p u t pulse rise -tim e: « 6 ns. In p u t p ulse vo ltag e: ,7V Features: • Input & Output ECL Buffered

Mdu 1517

Abstract: IC 8783 N
Contextual Info: data delay devieesYinc. Table of Contents Page C o m p a n y P r o f i l e .In s id e F ro n t C o v e r D C E le c tric a l C h a r a c t e r is t ic s . P ro d u c t S e l e c t i o n . 1

Contextual Info: Digital Delay Units SERIES DDU-12H 10 Taps ECL Interfaced Test Conditions: Features: • Input & Output ECL Buffered ■ 10 Equally Spaced Taps ■ PC Board Economy Achieved Specifications: ■ Total Delay Tolerance: ± 5% or better, or 2 ns whichever is greater.

Contextual Info: Digital Delay Units SERIES DDU-12H 10 Taps ECL Interfaced Test Conditions: Features: • Input & Output ECL Buffered ■ 10 Equally Spaced Taps ■ PC Board Economy Achieved Specifications: ■ Total Delay Tolerance: ± 5% or better, or 2 ns whichever is greater.

Contextual Info: MILITARY PRODUCTS Most of Data Delay Devices digital delay line products are available in military version. They are identified as follows: PWC-30 Example: M C3 Series Pulse Width Military Unit_ Case Dimensions The Military Delay Line Products Feature The Following:

Contextual Info: data vm delayW devicesYinc. Digital Delay Units SERIES DDU-12H 10 Taps ECL Interfaced Test Conditions: • ■ ■ ■ Features: ■ Input & Output ECL Buffered ■ 10 Equally Spaced Taps ■ PC Board Economy Achieved Specifications: ■ Total Delay Tolerance: ± 5% or better,

Contextual Info: MILITARY PRODUCTS Most of Data Delay Devices digital delay line products are available in military version. They are identified as follows: Example: PWC-30 35 M C3 Series Pulse Width. Military Unit_ Case Dimensions The Military Delay Line Products Feature The Following:

DU3C

Abstract: smd 312F TTL Logic Family list
Contextual Info: Table of Contents Page Company P r o file .Inside Front Cover Product List By F u n c tio n .2,3

pin IC 8783 n

Contextual Info: data delay devicesTinc. Table of Contents Page Page Company P r o file . Inside Front Cover Product S e le c tio n .1 List By , 3

DDU-12H-20

Abstract: 12h300
Contextual Info: data V?3<v> delay 'a devices; inc. Digital Delay Units SERIES DDU-12H 10 Taps ECL Interfaced Test Conditions: • ■ ■ ■ Input pulse-width: 150% of total delay. Input pulse rise-time: =s6 ns. Input pulse voltage: -,7 V Rise-time measured from 20% to 80% of