DDR2 SDRAM CONTROLLER Search Results

ddr phy

Contextual Info: DDR2-SDRAM-CTRL DDR/DDR2 SDRAM Memory Controller Megafunction The DDR2-SDRAM-CTRL megafunction provides a simplified, pipelined, burstoptimized interface to all industry-standard DDR and DDR-II SDRAM devices currently available, including Mobile DDR SDRAMs. It features:

verilog code for ddr2 sdram to virtex 5

Abstract: ddr phy 5VLX30-3
Contextual Info: DDR2-SDRAM-CTRL DDR/DDR2 SDRAM Memory Controller Core The DDR2-SDRAM-CTRL core provides a simplified, pipelined, burst-optimized interface to all industry-standard DDR and DDR-II SDRAM devices currently available, including Mobile DDR SDRAMs. It features:

nt5tu64m16hg

Abstract: NT5TU64M16HG-AC
Contextual Info: 1Gb DDR2 SDRAM H-Die DDR2 1Gb SDRAM Nanya Technology Corp. NT5TU128M8HE / NT5TU64M16HG NT5TU128M8HE / NT5TU64M16HG Commercial, Industrial and Automotive DDR2 1Gb SDRAM Features  JEDEC DDR2 Compliant  Data Integrity - Auto Refresh and Self Refresh Modes

NT5TU64M8BE-3C

Abstract: SCK 103 ntc NT1GT72U8PB0BN DDR2-667 PC2-5300 SSTL-18 NT512T72U89B0BN-3C NT2GT72U4NB0BN-3C Nanya DDR2 Nanya Technology
Contextual Info: NT512T72U89B0BN/ NT1GT72U8PB0BN / NT2GT72U4NB0BN 512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72 240pin DDR2 SDRAM Fully Buffered DIMM Based on 64Mx8 & 128Mx4 DDR2 SDRAM - B die Features • 512MB 64Mx72 DDR2 Fully Buffered DIMM based on 64Mx8 DDR2 SDRAM NT5TU64M8BE-3C .

NT5TU128M8

Abstract: NT5TU128M8HE-AC
Contextual Info: 1Gb DDR2 SDRAM H-Die DDR2 1Gb SDRAM Preliminary NT5TU128M8HE / NT5TU64M16HG Specifications and functions are not finalized!! Commercial, Industrial and Automotive DDR2 1Gb SDRAM Features  JEDEC DDR2 Compliant  Data Integrity - Auto Refresh and Self Refresh Modes

Contextual Info: NT1GT72B89D2BD / NT2GT72B8PD2BD NT1GT72B89D2BE / NT2GT72B8PD2BE 1GB: 128Mx72 / 2GB: 256Mx72 Draft 240pin DDR2 SDRAM Fully Buffered DIMM Based on 128Mx8 DDR2 SDRAM Features • 1GB 128Mx72 and 2GB 256Mx72 DDR2 Fully Buffered DIMM based on 128Mx8 DDR2 SDRAM NT5TU256M4BJ-37A/3B .

NT5TU64M8

Abstract: DDR2-667 PC2-5300 SSTL-18 NT5TU64M8AE-3C
Contextual Info: NT512T72U89ACBN NT1GT72U8PACBN NT2GT72U4NACBN 512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72 240pin DDR2 SDRAM Fully Buffered DIMM Based on 64Mx8 & 128Mx4 DDR2 SDRAM - A die Features • 512MB 64Mx72 DDR2 Fully Buffered DIMM based on 64Mx8 DDR2 SDRAM NT5TU64M8AE-3C .

8089 architecture

Abstract: Nanya Technology
Contextual Info: NT512T72U89B1BN/ NT1GT72U8PB1BN / NT2GT72U4NB1BN 512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72 240pin DDR2 SDRAM Fully Buffered DIMM Based on 64Mx8 & 128Mx4 DDR2 SDRAM - B die Features • 512MB 64Mx72 DDR2 Fully Buffered DIMM based on 64Mx8 DDR2 SDRAM NT5TU64M8BE-3C .

NT2GT72U4NB1BD-2C

Abstract: PC2-6400 SSTL-18 DDR2-800 Nanya Technology nanya 2Gb 800 NT5TU64M8BE-25C
Contextual Info: NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C 512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72 240pin DDR2 SDRAM Fully Buffered DIMM Based on 64Mx8 & 128Mx4 DDR2 SDRAM - B die Features • 512MB 64Mx72 DDR2 Fully Buffered DIMM based on 64Mx8 DDR2 SDRAM NT5TU64M8BE-25C .

DDR2 DIMM 240 pinout

Abstract: Nanya NT4GTT72U4PB1UD-3C NT5TU512T4BU DDR2 DIMM 240 pinout 4gb DDR2-667 PC2-5300 SSTL-18 Nanya Technology A6435
Contextual Info: NT4GTT72U4PB1UD-3C 4GB: 512Mx72 240pin DDR2 SDRAM Fully Buffered DIMM Based on 512Mx4 DDR2 SDRAM - B die Features • 4GB 512Mx72 DDR2 Fully Buffered DIMM based on 512Mx4 DDR2 SDRAM NT5TU512T4BU-3C . • JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line

DDR2 DIMM 240 pinout 4gb

Abstract: DDR2-800 PC2-6400 SSTL-18 NT5TU512T4BU NANYA Nanya Technology
Contextual Info: NT4GTT72U4PB1UD-2D 4GB: 512Mx72 240pin DDR2 SDRAM Fully Buffered DIMM Based on 512Mx4 DDR2 SDRAM - B die Features • 4GB 512Mx72 DDR2 Fully Buffered DIMM based on 512Mx4 DDR2 SDRAM NT5TU512T4BU-25D . • JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line

DDR PHY ASIC

Abstract: sdram verilog
Contextual Info:  Interfaces to all industry stan- DDR2-SDRAMCTRL DDR/DDR2 SDRAM Memory Controller Core The DDR2-SDRAM-CTRL core provides a simplified, pipelined, burst-optimized interface to all industry-standard DDR and DDR-II SDRAM devices currently available, including Mobile SDRAMs.

Nanya Technology

Abstract: DDR2-800 PC2-5300 PC2-6400 SSTL-18 512MX72 512Mx4 NT5TU512T4BU-3C
Contextual Info: NT4GTT72U4PB6UD-2D 4GB: 512Mx72 240pin DDR2 SDRAM Fully Buffered DIMM Based on 512Mx4 DDR2 SDRAM - B die Features • 4GB 512Mx72 DDR2 Fully Buffered DIMM based on 512Mx4 DDR2 SDRAM NT5TU512T4BU-3C . • JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line

DDR2 DIMM 240 pinout

Abstract: NT4GTT72U4PB1UN-3C DDR2-667 PC2-5300 SSTL-18
Contextual Info: NT4GTT72U4PB1UN-3C 4GB: 512Mx72 240pin DDR2 SDRAM Fully Buffered DIMM Based on 512Mx4 2x256Mx4 DDP DDR2 SDRAM - B die Features • 4GB 512Mx72 DDR2 Fully Buffered DIMM based on 512Mx4 DDR2 SDRAM (NT5TU512T4BU-3C). • JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line

DDR2 DIMM 240 pinout

Abstract: DDR2-667 NT4GTT72U4PB1UN-3C PC2-5300 SSTL-18 NT5TU512T4BU
Contextual Info: NT4GTT72U4PB1UN-3C 4GB: 512Mx72 240pin DDR2 SDRAM Fully Buffered DIMM Based on 512Mx4 2x256Mx4 DDP DDR2 SDRAM - B die Features • 4GB 512Mx72 DDR2 Fully Buffered DIMM based on 512Mx4 DDR2 SDRAM (NT5TU512T4BU-3C). • JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line

EP2C35F672C6

Abstract: vhdl code for ddr2 EP2C35 SSTL-18 vhdl code for uart EP2C35F672C6 altera board
Contextual Info: Using DDR/DDR2 SDRAM With SOPC Builder Application Note 398 August 2006, ver. 1.1 Introduction The DDR/DDR2 SDRAM Controller MegaCore function version 3.4.0 and later supports SOPC Builder, enabling the function to instantiate a DDR/DDR2 SDRAM Controller inside an SOPC Builder system.

Contextual Info: November 2007 HYS72T512420EFD–25F–C HYS72T512420EFD–3S–C 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev.1.10 Internet Data Sheet HYS72T512420EFD–[25F/3S]–C Fully-Buffered DDR2 SDRAM Modules

DDR2-400

Abstract: DDR2-533 DDR2-667 DDR2-800
Contextual Info: DDR2 Device Operations & Timing Diagram DDR2 SDRAM Device Operation & Timing Diagram 1 DDR2 Device Operations & Timing Diagram Contents 1. Functional Description 1.1 Simplified State Diagram 1.2 Basic Function & Operation of DDR2 SDRAM 1.2.1 Power up and Initialization

Contextual Info: July 2008 HYS72T512920EFA–3S 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.10 Internet Data Sheet HYS72T512920EFA–3S Fully-Buffered DDR2 SDRAM Modules Revision History: Rev. 1.10, 2008-07-21 All

sdram controller

Abstract: controller for sdram DDR2 pin out AMD64
Contextual Info: DDR & DDR2 SDRAM Controller October 2005, Compiler Version 3.3.0 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.0 contain the following information: • ■ ■ ■ ■ ■ System Requirements To use DDR and DDR2 SDRAM Controller Compiler version 3.3.0, the

HYS72T512920EFA

Abstract: 03032008-C7XS-WKOI HYS72T
Contextual Info: February 2008 HYS72T512920EFA–3S–C2 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.00 Internet Data Sheet HYS72T512920EFA–3S–C2 Fully-Buffered DDR2 SDRAM Modules Revision History: Rev. 1.00, 2008-02-07

Contextual Info: June 2008 HYS72T1G542EFA–25F–C2 HYS72T1G542EFA–3S–C2 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM EU RoHS Compliant Products Advance Internet Data Sheet Rev.0.62 Advance Internet Data Sheet HYS72T1G542EFA–[25F/3S]–C2 Fully-Buffered DDR2 SDRAM Modules

Contextual Info: Aug 2008 HYS72T1G542EFA–3S–C2 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM EU RoHS Compliant Products Internet Data Sheet Rev.1.00 Internet Data Sheet HYS72T1G542EFA–3S–C2 Fully-Buffered DDR2 SDRAM Modules Revision History: Rev.1.00, 2008-08-28

Contextual Info: May 2008 HYS72T512920EFA–3S 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.01 Internet Data Sheet HYS72T512920EFA–3S Fully-Buffered DDR2 SDRAM Modules Revision History: Rev. 1.01, 2008-05-14 Page 25