DDR1 Search Results

micron ddr3

Abstract: DDR3 timing diagram DDR3 model verilog codes Verilog DDR3 memory model micron memory model for ddr3 MT41J128M8 Verilog DDR memory model DDR3 "application note" DDR3 DQ flip flop IC
Contextual Info: Maxim > Design Support > App Notes > T/E Carrier and Packetized > APP 5120 Keywords: DDR1, DDR3, jitter, buffer, TDMoP, TDM over packet, DDR, SDRAM, PDV, PSN, double data rate APPLICATION NOTE 5120 Aug 26, 2011 Using a DDR3 Memory Module with the DS34S132

AIC1383

Abstract: AIC1383CSTR AIC1383PSTR CES7002A MS-012AA
Contextual Info: AIC1383 1.5A Termination Regulator FEATURES DESCRIPTION 1.5A Source and Sink Current Ability AIC1383 linear regulator is designed to achieve 1.5A source and sink current while regulating an output voltage to within 25mV. Support DDR1 1.25VTT and DDR2 (0.9VTT)

Contextual Info: SC486 Complete DDR1/2 Memory Power Supply POWER MANAGEMENT Description Features The SC486 is a combination switching regulator and linear source/sink regulator intended for DDR1/2 memory systems. The switching regulator is used to generate the supply voltage, VDDQ, for the memory system. It is a

Contextual Info: SC1486A NOT RECOMMENDED FOR NEW DESIGN Complete DDR1/2/3 Power Supply Controller POWER MANAGEMENT Description Features ‹ 1% DC accuracy ‹ Compatible with DDR1, DDR2 and DDR3 memory The SC1486A is a dual output constant on-time synchronous buck PWM controller optimized for cost

SC488MLTRT

Abstract: SC488ML
Contextual Info: SC488 Complete DDR1/2/3 Memory Power Supply POWER MANAGEMENT Description Features The SC488 is a combination switching regulator and linear source/sink regulator intended for DDR1/2 memory systems. The purpose of the switching regulator is to generate the supply voltage, VDDQ, for the memory system.

ddr 184 pin

Abstract: SLOT DIMM 184-pin ae1a2 DDR110-27T7RL DDR110-56T7RL TSSOP24
Contextual Info: DDR110-xxT7RL ASD IPAD™ Computer DOUBLE DATA RATE TERMINATION NETWORK WITH DISABLE SWITCH MAIN APPLICATION DDR double data rate Termination Network used on. • Motherboard ■ Workstation ■ Server ■ Notebooks 24 1 12 DESCRIPTION The DDR110 provides 10 bits resistor Network to

Contextual Info: DDR12 Series Dual output DC-DC CONVERTERS Tracking Dual Output 1 NEW Product • High current dual-output power module for DDR memory • Single compact module provides 25 A @ 2.5 V for Vddq supply and 8 A @ 1.25 V for Vtt termination • Tracking dual output voltages 1.25 V @ 8 A, 2.5 V @ 25 A

Contextual Info: M34E02 M34E02-F 2 Kbit serial presence detect SPD EEPROM for double data rate (DDR1 and DDR2) DRAM modules Features • 2 Kbit EEPROM for DDR1 and DDR2 serial presence detect ■ Backward compatible with the M34C02 ■ Permanent and reversible software data

CXK77Q18162GB

Abstract: CXK77Q18162GB-25 CXK77Q18162GB-27 CXK77Q18162GB-3 CXK77Q36162GB CXK77Q36162GB-25 CXK77Q36162GB-27 CXK77Q36162GB-3
Contextual Info: SONY CXK77Q36162GB / CXK77Q18162GB 16Mb DDR1 HSTL High Speed Synchronous SRAMs 512K x 36 or 1M x 18 25/27/3 Preliminary Description The CXK77Q36162GB (organized as 524,288 words by 36 bits) and the CXK77Q18162GB (organized as 1,048,576 words by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

Contextual Info: DDR12 SERIES Embedded Power for Business-Critical Continuity Dual Output Rev.09.05.07 ddr12 series 1 of 11 DDR12 SERIES Total Power: W Input Voltage: 10.8 - 13.2 VDC # of Outputs: Dual Special Features • High current dual-output power module for DDR memory

JESD51-2

Abstract: flotherm samsung ddr theta JA JESD51-X DDR flotherm
Contextual Info: DDR1 Ind. Thermal application Purpose ‰ ‰ ‰ Test Method This document provides a general range of thermal for ensuring that Samsung DDR Industrial Temp. memory does not exceed the maximum allowable temperature. And defines Ta and Tj value for reliability and functionality of DDR

AAAC

Contextual Info: April 2004 ASM4SSTVF16857 rev 1.1 DDR 14-Bit Registered Buffer LVCMOS level at a valid logic state since VREF may Features • not be stable during power-up. Fully JEDEC JC40 - JC42.5 compliant for DDR1 applications to include: PC1600, PC2100, PC2700 To ensure that outputs are at a defined logic state

IRF7811AV

Abstract: JESD51-1 JESD51-2 JESD51-7 J-STD-020B SC1486A SC1486AEVB SC1486AITSTR SC1486AITSTRT TSSOP-28
Contextual Info: SC1486A Complete DDR1/2/3 Power Supply Controller POWER MANAGEMENT Description Features ‹ 1% DC accuracy ‹ Compatible with DDR1, DDR2 and DDR3 memory The SC1486A is a dual output constant on-time synchronous buck PWM controller optimized for cost effective mobile DDR1, DDR2 and DDR3 applications.

stmicroelectronics "serial eeprom"

Abstract: JESD22-A114A M34C02 M34E02
Contextual Info: M34E02 2 Kbit serial presence detect SPD EEPROM for double data rate (DDR1 and DDR2) DRAM modules Features • 2 Kbit EEPROM for DDR1 and DDR2 serial presence detect ■ Backward compatible with the M34C02 ■ Permanent and reversible software data protection for lower 128 bytes

Contextual Info: Datasheet 1.0V to 5.5V, 1A 1ch Termination Regulators for DDR-SDRAMs BD3539FVM BD3539NUX General Description Key Specifications          BD3539 is a termination regulator that complies with JEDEC requirements for DDR1-SDRAM, DDR2-SDRAM, and DDR3-SDRAM. This linear power

Contextual Info: Datasheet Regulator IC Series for Automotive Termination Regulator for DDR-SDRAMs BD35395FJ-M General Description Key Specifications         BD35395FJ-M is a termination regulator compatible with JEDEC DDR1/2/3/3L-SDRAM, which functions as a linear

AIC1383B

Abstract: AIC1383BCE5TR AIC1383BPE5TR CES7002A TO263-3 package DS-1383
Contextual Info: AIC1383B 3A Termination Regulator FEATURES DESCRIPTION 3A Source and Sink Current Ability AIC1383B linear regulator is designed to achieve 3A source and sink current while regulating an output voltage to within 45mV. Support DDR1 1.25VTT and DDR2 (0.9VTT)

DDR1215DT

Contextual Info: DDR1215DT Linear ICs dc-to-dc/Charge Pump Voltage Converter status Military/High-RelN Output Voltage Nominal V 15ñ Load Current Max. (A)100m Drop-Out Volt Max. P(D) Max. (W)3 Nom. Supp (V)12 Minimum Operating Temp (øC)-20 Maximum Operating Temp (øC)70

DDR1205S

Contextual Info: DDR1205S Linear ICs dc-to-dc/Charge Pump Voltage Converter status Military/High-RelN Output Voltage Nominal V 5 Load Current Max. (A)500m Drop-Out Volt Max. P(D) Max. (W)2.5 Nom. Supp (V)12 Minimum Operating Temp (øC)-20 Maximum Operating Temp (øC)70 Package StyleDIP

Contextual Info: VCN60/70 Series High Efficiency, High Current Density, 60 or 70 Amp Single Inline Package DC/DC Converters DESCRIPTION Designed to support DDR1, DDR2 and DDR3 SDRAM memory power requirements, the VCN60/70 Series point-of-load, non-isolated DC/DC converters have the high performance

BD3539FVM

Abstract: BD3539 ic 7490 pin diagram BD3539NUX ic 7495 working pin internal structure of 7490 IC IC 7490 pin configuration 7490 IC CHIP internal diagram of 7490 IC ic 7490 internal diagram
Contextual Info: Hi-performance Regulator IC Series for PCs Termination Regulators for DDR-SDRAMs BD3539FVM,BD3539NUX No.09030EAT24 Description BD3539FVM/NUX is a termination regulator compatible with JEDEC DDR1-SDRAM, DDR2-SDRAM, DDR3-SDRAM which functions as a linear power supply incorporating an N-channel MOSFET and provides a sink/source current capability up to

ddr3 MTBF

Abstract: SENSE23 4sp560m t
Contextual Info: VCN60/70 Series www.murata-ps.com High Efficiency, High Current Density, 60 or 70 Amp Single Inline Package DC/DC Converters DESCRIPTION ESCRIPTIO ON Designed signed to su support upport DDR1 DDR1, 1, DDR2 and DDR3 SDRA SDRAM AM memoryy power requ requirements,

Contextual Info: Hi-performance Regulator IC Series for PCs Termination Regulators for DDR-SDRAMs BD3539FVM,BD3539NUX No.09030EAT24 Description BD3539FVM/NUX is a termination regulator compatible with JEDEC DDR1-SDRAM, DDR2-SDRAM, DDR3-SDRAM which functions as a linear power supply incorporating an N-channel MOSFET and provides a sink/source current capability up to

Contextual Info: SONY CXK77Q36162GB 25/27/3 Preliminary 16Mb DDR1 HSTL High Speed Synchronous SRAM 512K x 36 Description The CXK77Q36162GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 524,288 words by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a two-deep write buffer