DDR PHY ASIC Search Results

ddr phy

Abstract: DDR PHY ASIC LSI Rapidchip CW000722 CW761041 g12 DDR lsi CW761030
Contextual Info: RapidReady DDR-1 SDRAM Physical Layer Core CW761041 & CW000722 OVERVIEW FEATURES LSI Logic’s DDR-I physical layer core (PHY core) provides an integrationfriendly physical layer interface between the memory controller logic of the ASIC and the data and address busses of DDR-I SDRAM memory (see Figure1).

MPC83xx, linux

Abstract: MPC8568E MPC8568 QUICC Engine
Contextual Info: MPC8568E Processor Board Block Diagram SODIMM DDR 72-bit 256 MB @ 533 MHz Data Rate From IO Board COP 16-pin LEDs I2C DIP-Switch Config Clock RJ-45 2x eTSEC Quad 10/100/1000 Ethernet PHY RJ-45 RJ-45 RJ-45 RJ-45 2x RS232 RJ-45 RJ-45 I2C2 Bus DUART 18V 10V DDR Core

CS200

Abstract: 65nm DDR PHY ASIC HDMI to lvttl cmos logic 90nm DAC 90nm CS200A 65-NM UHS SD Card Hdmi to micro usb wiring
Contextual Info: 65nm CMOS Standard Cell Leakage Current Large CS200 ASIC Series Server/ Network Low Power Power Low Lineup Lineup CS200LL CS200A HV-Tr DHV-Tr HS-Tr Mo C Mobile STD-Tr STD-Tr LL-Tr Computing High End Server HighHigh Performance Performance Lineup LineupCS200HP

DDR PHY ASIC

Abstract: CX3000 CX5000 CX6100 PLL in RTL ARM926EJ BA12 BA22 cx-5900 ASIC USB 2.0
Contextual Info: ChipX Offers Analog and Mixed-Signal ASIC Excellence ChipX, Inc. is a leading Analog and M ixed-Signal ASIC com pany with unique technology that allows you to reduce the cost, developm ent cycle and risk associated with com plex SoC/ASIC designs. ChipX brings more than 22 years of experience to the A SIC m arket

CX6100

Abstract: DDR PHY ASIC CX6104 CX61 CX6113 CHIPX CX6119 cx6112 tca 765
Contextual Info: Product Brief CX6100 Structured ASIC with PCI Express Product Description The CX6100 product family combines a built-in, silicon-proven, industry standard PHY for PCI Express with the well-proven X-Cell architecture, to provide industry leading performance

ALTMEMPHY

Abstract: ddr phy DDR PHY ASIC DDR3 jedec h1l1
Contextual Info: External Memory PHY Interface ALTMEMPHY (nonAFI) Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01014-7.3 Software Version: Document Version: Document Date: 9.1 SP1 7.3 January 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words

atmel h020

Abstract: atmel h022 uart baud rate spear AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022 Atmel ARM9 ATMEL 0905
Contextual Info: SPEAR-09-H022 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates

atmel h020

Abstract: M25Pxxx state machine for ahb to apb bridge multiport memory controller A13 cristal ARM926EJ-S electrical ATMEL 0905 INPUT/atmel h020
Contextual Info: SPEAr-09-H020 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates with

ISSP90-STD

Abstract: Ethernet-MAC ic ISSP90 TBGA-420 FC-BGA729
Contextual Info: New ASIC Solution Platform TM ISSP ISSP1 Series ISSP90 Series ISSP1-STD Series ISSP1-HSI Series ISSP90-STD Series ISSP90-HSI Series ore> , easily, f e B n kly See c i r e u v q e d form N LSIs realize t a l P <A New erformance p - High- low cost and at NEC Electronics

ddr phy interface

Abstract: AN-550-2 module AN-550
Contextual Info: AN 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs AN-550-2.0 March 2010 This application note describes how to implement the delay-locked loop DLL phase offset feature with Altera Stratix® FPGAs and HardCopy® ASICs. Introduction

DDR PHY ASIC

Abstract: SiI 3012 satalink sata phy pioneer pll
Contextual Info: SiI 3012 SATALink 2-Port PHY The SiI 3012 is a dual-channel Serial ATA SATA PHY featuring Silicon Image's SATALiteTM interface. The SiI 3012 is compliant with the Gen 1 (1st generation) Serial ATA specification, with each port capable of independently transmitting and receiving data at the full 1.5 Gbps rate.

E300

Abstract: MPC8360E MPC8548 mgw hardware DDR Controller 802.16e wimax chip hardware MGW
Contextual Info: Application Summary Line Card in 802.16 WiMAX Wireless Equipment Using the PowerQUICC II Pro MPC8360E The IEEE-defined 802.16 standards are designed to ensure an always-on wireless 802.16 LINE CARD/SINGLE SECTOR BS HIGH-LEVEL ARCHITECTURE broadband data connection for both fixed (first

Contextual Info: SPEAR-09-H020 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC DATA BRIEF Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates with 8 channels internal DMA high speed

SAS controller chip

Abstract: Emulex SAS controller multi protocol serial controller
Contextual Info: IOC 500S Complete Embedded Flexibility Embedded Storage Controllers High Performance SAS IOC The Emulex IOC 500S is the SAS I/O Controller member of Emulex’s driver compatible multiprotocol ASIC family designed for storage system providers that want flexibility in their

736-Pin

Abstract: LSI coreware library 64X144
Contextual Info: ADVANCE DATASHEET RC1800 Foundation Slice Family July 2005 The RapidChip RC1800 Foundation Platform ASIC Family, except for the RC1812 slice, is in NO-NEW-DESIGN Status as of July 2005. LSI Logic is not accepting new designs in this slice Family. Information in this datasheet is

stratix2

Abstract: AN328 EP2SGX90FF1508C3
Contextual Info: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices Application Note 449 September 2007, v1.2 Introduction Stratix II and Stratix II GX devices offer support for double data rate DDR memories, such as DDR2/DDR SDRAM, QDRII+/QDRII SRAM,

Contextual Info: SPEAR-09-H022 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC DATA BRIEF Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates 16K LUT equivalent with 8 channels internal

EP3C16F484C6

Abstract: vhdl code hamming ecc hynix ddr3 vhdl coding for hamming code ALTMEMPHY vhdl code HAMMING LFSR EP2S60F1020C3 EP3SL110F1152C2 vhdl code hamming
Contextual Info: Section I. DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_DDR_UG-1.3 Document Version: Document Date: 1.3 February 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

vhdl code hamming

Abstract: DDR3 ECC SODIMM vhdl code hamming ecc vhdl code for ddr2 DDR SDRAM Controller look-ahead policy ddr2 ram ddr phy ddr2 ram slot pin detail EP3C16F484C6 DDR2 SDRAM ECC datasheet and Application Note
Contextual Info: Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_DDR_UG-2.0 Document Version: Document Date: 2.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

RGMII to MII glueless connection

Abstract: MPC8560 tsec application MPC8560 tsec interrupt MPC8560 tsec rgmii configuration MPC8560 tsec gmii configuration 3g router MPC8260 MPC8560 MPC860T coherency module
Contextual Info: Freescale Semiconductor, Inc. Technical Summary MPC8560TS/D Rev. 0.6 7/2002 Freescale Semiconductor, Inc. MPC8560 Power QUICC III  Integrated Communications Processor The MPC8560 PowerQUICC III is a next-generation PowerQUICC II integrated communications processor. The MPC8560 provides integration of

QFN-88

Abstract: CX6212 88 qfn DDR PHY ASIC CX6210 1602 KB lcd CHIPX LCD 1602 PLL in RTL Structured
Contextual Info: Product Brief CX6200 Structured ASIC with USB 2.0 PHY Product Description The CX6200 product family—a member of the latest generation of Structured ASICs from ChipX—combines built-in, silicon-proven, industry standard PHYs for USB 2.0 High Speed On-the-Go OTG with the well-proven X-Cell Structured ASIC architecture to provide industry

atmel h020

Abstract: atmel h022 atmel 0713 0x16000000 Atmel PART DATE CODE AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022
Contextual Info: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates 16K LUT equivalent with 8 channels internal

POWERPC E500

Abstract: POWERPC E500 instruction set MPC8560 tsec interrupt rgmii specification 3g router MPC8260 MPC8540 MPC8560 MPC860T MPC8560 pci interrupt
Contextual Info: Freescale Semiconductor, Inc. Advance Information MPC8560PB Rev. 0, 12/2003 Freescale Semiconductor, Inc. MPC8560 PowerQUICC III Integrated Communications Processor Product Brief The MPC8560 PowerQUICC III™ is a next-generation PowerQUICC II™ integrated

atmel h020

Abstract: atmel 0713 ATMEL 620 spear linux uart baud rate spear AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022
Contextual Info: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates