DDR JP Search Results

SC3682

Abstract: SRN21C SRN25B IT8705F ITE8705F ITE IT8705F RN75C RN73B 1762AA SRN28B
Contextual Info: A B C D Table of Contents Revision History EFFICEON DDR Interface EFFICEON AGP Interface EFFICEON HT Interface EFFICEON Core Power EFFICEON 2.5 & 3.3V Pwr EFFICEON 1.2 & 1.5V Pwr DDR SO-DIMM 1 1/2 DDR SO-DIMM 1 (2/2) DDR SO-DIMM 2 (1/2) DDR SO-DIMM 2 (2/2)

Contextual Info: LP2998 LP2998 DDR-I and DDR-II Termination Regulator Literature Number: SNVS521G LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of

LP2998

Abstract: LP2998MA LP2998MAE LP2998MAX LP2998MR LP2998MRE LP2998MRX M08A SSTL-18
Contextual Info: LP2998 DDR-II and DDR-I Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot

Contextual Info: LP2998 DDR-II and DDR-I Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot

LP2998

Abstract: LP2998MA LP2998MAX LP2998MR LP2998MRX M08A SSTL-18
Contextual Info: LP2998 DDR-II and DDR-I Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot

CMI9880

Abstract: OZ2216 LID591 AOS4916 CH747 24LC02A Socket AM2 HP multibay ALC880D M5285
Contextual Info: 1 2 3 AC/BATT CONNECTOR PG 42 A 4 5 6 DC/DC Dothan/Yonah 7 CLOCKS +1.05V/+1.5V +1.8V/+0.9V PG 37~41 +3V/+5V 478 Micro-FCPGA it c a PG 42 +1.05V +1.8VSUS B Alviso 400/533 MHZ DDR II DDR-SODIMM1 PG 10,11 +1.8VSUS 400/533 MHZ DDR II h c +2.5V DDR-SODIMM2 PG 10,11

LP2996MX

Abstract: LP2996
Contextual Info: LP2996 LP2996 DDR Termination Regulator Literature Number: SNOSA40H LP2996 DDR Termination Regulator General Description Features The LP2996 linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide

Contextual Info: LP2997 LP2997 DDR-II Termination Regulator Literature Number: SNVS295D LP2997 DDR-II Termination Regulator General Description Features The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to

ECJ1VC1H101K

Abstract: l 5010 mh A114 A115 JESD22 JESD78 NCP5214A NCP5214AMNR2G V1836 smd schottky diode marking s4
Contextual Info: NCP5214A 2−in−1 Notebook DDR Power Controller The NCP5214A 2−in−1 Notebook DDR Power Controller is specifically designed as a total power solution for notebook DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of linear

ECJ1VC1H101K

Abstract: smd diode sod-123 marking code a7 ECJ2FB1C475M smd schottky diode s4 SOD-123 A114 A115 JESD22 JESD78 NCP5218 NCP5218MNR2G
Contextual Info: NCP5218 2−in−1 Notebook DDR Power Controller The NCP5218 2−in−1 Notebook DDR Power Controller is specifically designed as a total power solution for notebook DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of linear

ECJ1VC1H101K

Abstract: A114 A115 JESD22 JESD78 MBR0530T1 NCP5214 NCP5214MNR2G Diode smd marking A7 sod-123 diode marking A7 SOD123
Contextual Info: NCP5214 2−in−1 Notebook DDR Power Controller The NCP5214 2−in−1 Notebook DDR Power Controller is specifically designed as a total power solution for notebook DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of linear

Contextual Info: NCP5218 2−in−1 Notebook DDR Power Controller The NCP5218 2−in−1 Notebook DDR Power Controller is specifically designed as a total power solution for notebook DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of linear

Contextual Info: NCP5214 2−in−1 Notebook DDR Power Controller The NCP5214 2−in−1 Notebook DDR Power Controller is specifically designed as a total power solution for notebook DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of linear

Contextual Info: NCP5214A 2−in−1 Notebook DDR Power Controller The NCP5214A 2−in−1 Notebook DDR Power Controller is specifically designed as a total power solution for notebook DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of linear

fet B20 p03

Abstract: m7101 M1535 a1 MAXIM 1535 CE KB3886 VT6202 amtek HK-AE-15A1R0 p1488 VIA VT6202
Contextual Info: 5 4 3 2 1 Charge & Selector PAGE 28 PWRGD & ENABLEVIO Circuit D ROM & CMS PAGE 34 System Power 5V & 3V MAX1632 TABLET PC - T01 BLOCK DIAGRAM PAGE 8 Vcore Power Maxim 1718 PAGE 30 DEBUG TDM Port PAGE 33 VGA & DDR Power D PAGE 8 DDR PAGE 31 DDR on Board CRUSOE

CX20468-31

Abstract: CX20468 MC9701 RS480M hp pavilion r62 hp pavilion g6 u2343 KBC-NS87551L IR7832 MFB902
Contextual Info: 1 2 3 4 5 6 PCB STACK UP LAYER 2 : GND A DDR-SODIMM1 CLAW HAMMER / RS480 / SB400 CPU THERMAL SENSOR DDR 266,333,400MHz GMT-781 CPU CLAW HAMMER LAYER 4 : IN2 LAYER 5 : VCC 8 CT8 BLOCK DIAGRAM LAYER 1 : TOP LAYER 3 : IN1 7 14.318MHz 754 Pins uPGA DDR-SODIMM2

smd diode a6u

Abstract: SIS M760GX M760GX RN75E sis964L rn73e asus tl494 "SiS964L" Q33B
Contextual Info: 5 4 3 2 1 FILE LIST THERMAL A6U BLOCK DIAGRAM D +3.3VS 08 13 DDR TERMINATION 07 +1.25V 06 +2.5V +2.6V AMD K8 FAN DUAL DDR SODIMM DDR +VCORE,+2.5V(+2.6V), +1.25V, +2.5VS, +1.2VS +5VS 03 36 04 05 Hyper Transport 16 x 16 CLOCK GEN LVDS LCD 14 302LV +3.3VS SIS M760GX

"DDR1 SDRAM"

Abstract: 0773 LP2998 LP2998MA LP2998MAE LP2998MAX LP2998MR LP2998MRE LP2998MRX M08A
Contextual Info: LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR1-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot

LP2998

Abstract: LP2998MA LP2998MAE LP2998MAX LP2998MR LP2998MRE LP2998MRX M08A SSTL-18
Contextual Info: LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR1-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot

CMI9761A

Abstract: 150w bass circuit IRDC357 CB3051 SiS648FX max1546 CB346 CCS C TOUCHPAD CIRCUIT 648FX AUD101
Contextual Info: 5 4 3 2 1 SYS POWER G900 SYSTEM BLOCK Diagram P4 CPU D D VGA OUT CPU VCORE DDR NB DDR-400 POWER-PLANE DC JACK & CHARGER AGP 8X AUX POWER 17" LCD Wild Screen A G P M10/M11 Daughter Card S-Video TV OUT USB P6 MCE DDR POWER FSB 800MHz SODIMM HyperZIP 133MHz PCI BUS

LP2998

Abstract: LP2998MA LP2998MAE LP2998MAX LP2998MR LP2998MRE LP2998MRX M08A SSTL-18
Contextual Info: LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR1-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot

P4N266

Abstract: VT8233 quanta ic ck1 160v p10 cpu c644 100v 27p csp c613 10m 27p AD127 QUANTA GD1 P4X266 a71 c21 100v 27p
Contextual Info: 1 2 3 4 5 6 7 8 EF4 A A CLOCKS Northwood AC/BATT CONNECTOR CY28347 Panel Connector Page:27 Page:10 Micro-FCPGA BATT CHARGER Page : 2, 3 LVDS IC DC/DC Page:27 GFPD[0.35] B B DDR-SODIMM1 VIA P4N266 266MHZ DDR Page:11 664 BGA Page:4,5,6 DDR-SODIMM2 S-Video

RTS5158

Abstract: P2231TF G993P1UF ms-16321 MS-163B1 MAX8774GTL RST5158 ATI sb600 amd fm2 socket pin diagram MS16321
Contextual Info: 1 A COVER SHEET Block Diagram POWER DELIVERY CHART CLOCK DISTRIBUTION I2C ILLUSTRATE AMD S1 HT & CTRL I/F AMD S1 DDR II Memory I/F AMD S1 Power & GND DDR II A/B SO-DIMM CONN. DDR II A/B Terminations RS690M HT LINK I/F RS690T PCI-E LINK&HDMI I/F RS690T SYSTEM I/F&CLK

Contextual Info: LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR1-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot