DCM 10 GBPS Search Results

XAPP623

Contextual Info: POS-PHY Level-4 Core v5.0 DS209 August 7, 2002 Product Specification LogiCORE Facts Features • Fully compliant with OIF-SPI4-02.0 System Packet Interface Level-4 SPI-4 Phase 2 standard • Supports POS, ATM, and Ethernet 10 Gbps applications • Delivered through CORE Generator providing easy

BF957

Abstract: FF1152 FG676
Contextual Info: SPI-4.2 Core v6.0.1 DS209 October 10, 2003 Features Product Specification LogiCORE Facts • Fully compliant with OIF-SPI4-02.0 System Packet Interface Level-4 SPI-4 Phase 2 standard • Supports POS, ATM, and Ethernet 10 Gbps applications • Sink and Source cores selected and configured

ld800

Abstract: Multi-Channel dispersion compensation module specifications LD400 Dispersion Compensation Module LDP30 ld1600 80-KM DCM 10 gbps 80km
Contextual Info: WDM & Optical Transport Datasheet LambdaDriver - Dispersion Compensation Module EM800/1600-DCM and DCMD Features 80 km dispersion compensation for DWDM networks Covers all C-band DWDM channels Insertion loss 5db Available as single DCM (EM800-DCM and EM1600DCM), or dual DCM in one LD module (EM800-DCMD

MDIO clause 45

Abstract: SCAN25100 NSC crystal 30.72MHz K28-1 remote transmiter BTS 5010 AVDD33 SCAN12100 SCAN12100TYA TQFP-100
Contextual Info: SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement • DCM also measures chip and other delays to ≤ ± 1200 ps General Description The SCAN12100 is a 1228.8 and 614.4 Mbps serializer/deseralizer SerDes for high-speed bidirectional serial data

BTS 5010

Abstract: MDIO clause 45 AVDD33 SCAN25100 SCAN25100TYA TQFP-100 ask transmiter 78 los 802.3ae MDIO remote transmiter
Contextual Info: SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement • DCM also measures chip and other delays to ≤ ± 1200 ps General Description The SCAN25100 is a 2457.6, 1228.8, and 614.4 Mbps serializer/deseralizer SerDes for high-speed bidirectional serial

4x4 unsigned multiplier VERILOG coding

Abstract: vhdl code for lvds driver 80C31 instruction set 4x4 signed multiplier VERILOG coding image enhancement verilog code verilog code of 4 bit magnitude comparator XC2V1000 Pin-out vhdl code of 32bit floating point adder verilog code for stop watch VHDL CODE FOR HDLC controller
Contextual Info: R Chapter 2 Design Considerations 1 Summary This chapter covers the following topics: • Using Global Clock Networks • Using Digital Clock Managers DCMs • Using Block SelectRAM Memory • Using Distributed SelectRAM Memory • Using Look-Up Tables as Shift Registers (SRLUTs)

MDIO clause 45

Abstract: HF RFID loop antenna design BTS 5010 MDIO clause 45 specification remote control transmiter
Contextual Info: SCAN25100 SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement Literature Number: SNLS223B SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement

UG331

Abstract: CWda04 XAPP256 manual SPARTAN-3 XC3S400 evaluation kit vhdl code for rs232 receiver hcl l21 usb power supply circuit diagram hcl p38 CIRCUIT diagram R80515 XC3SD1800A-FG676 vhdl ethernet spartan 3a
Contextual Info: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.6 December 3, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

RGMII constraints

Abstract: SGMII RGMII bridge fpga rgmii ipad data sheet rgmii specification 1000BASE-X Xilinx SPARTAN 3e
Contextual Info: LogiCORE IP 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009 R R Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You

RX-6 TX-6

Abstract: DS209 IXP2800 ML450 ML550 VIRTEX-5 DDR PHY DCM02
Contextual Info: SPI-4.2 v8.4 DS209 August 8, 2007 Product Specification Introduction LogiCORE Facts Core Specifics Device Family Alignment Type Performance Mbps /Speed LUT/Flop Pairs 64-bit static 622–700/-1,-2,-3 Rx: 2000 Tx: 2600 Rx: 6 Tx: 6 128-bit static 622–700/-1,-2,-3

manual SPARTAN-3 XC3S400 evaluation kit

Abstract: hcl l21 usb power supply circuit diagram verilog code for Modified Booth algorithm vhdl code for lcd of spartan3E UG331 TT 2222 Horizontal Output Transistor pins out dia verilog for 8 point fft using FPGA spartan3 vhdl code for ldpc decoder types of multipliers ge fanuc cpu 331
Contextual Info: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.7 August 19, 2010 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development

Contextual Info: SCAN12100 www.ti.com SNLS245D – SEPTEMBER 2006 – REVISED MAY 2008 SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement Check for Samples: SCAN12100 FEATURES 1 • 2 • • • • • • • • Exceeds LV and HV CPRI voltage and jitter

vhdl code for lcd of spartan3E

Abstract: verilog code for Modified Booth algorithm vhdl code for rs232 receiver ge fanuc cpu 331 ug331 vhdl ethernet spartan 3a spartan 3e vga ucf barco 16 BIT ALU design with verilog/vhdl code TUTORIALS xilinx FFT
Contextual Info: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.5 January 21, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

Contextual Info: SCAN12100 www.ti.com SNLS245E – SEPTEMBER 2006 – REVISED APRIL 2013 SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement Check for Samples: SCAN12100 FEATURES DESCRIPTION • The SCAN12100 is a 1228.8 and 614.4 Mbps

MDIO clause 45

Contextual Info: SCAN25100 www.ti.com SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013 SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement Check for Samples: SCAN25100 FEATURES DESCRIPTION • The SCAN25100 is a 2457.6, 1228.8, and 614.4

mimo antenna

Contextual Info: SCAN12100 www.ti.com SNLS245E – SEPTEMBER 2006 – REVISED APRIL 2013 SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement Check for Samples: SCAN12100 FEATURES DESCRIPTION • The SCAN12100 is a 1228.8 and 614.4 Mbps

Contextual Info: SCAN25100 www.ti.com SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013 SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement Check for Samples: SCAN25100 FEATURES DESCRIPTION • The SCAN25100 is a 2457.6, 1228.8, and 614.4

Contextual Info: SCAN25100 www.ti.com SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013 SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement Check for Samples: SCAN25100 FEATURES DESCRIPTION • The SCAN25100 is a 2457.6, 1228.8, and 614.4

Contextual Info: SCAN25100 www.ti.com SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013 SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement Check for Samples: SCAN25100 FEATURES DESCRIPTION • The SCAN25100 is a 2457.6, 1228.8, and 614.4

Virtex-II Pro xc2vp70ff1517

Abstract: XC2VP100 xc2vp40ff1148 XC2VP100FF1704 xilinx Xilinx XC2VP30-FF896 XC2VP70 XC2VP20-5 XC2VP30-FF896 speed XAPP623 XAPP653
Contextual Info: `6 52 Virtex-II Pro Platform FPGAs: DC and Switching Characteristics R DS083-3 v3.1.1 March 9, 2004 Product Specification Virtex-II Pro Electrical Characteristics Virtex-II Pro devices are provided in -7, -6, and -5 speed grades, with -7 having the highest performance.

DS1103

Abstract: LVCMOS25 LVCMOS33 XAPP623 XAPP653 XAPP659 XAPP689 LVDCI33 XC2VPX70 XC2VPX20
Contextual Info: `6 48 Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics R DS110-3 v1.1 March 5, 2004 Advance Product Specification Virtex-II Pro X Electrical Characteristics Virtex-II Pro X devices are provided in -7, -6, and -5 speed grades, with -7 having the highest performance.

XC2VP125

Abstract: XC2VP50 XC2VP100 XC2VP70
Contextual Info: `6 Virtex-II Pro Platform FPGAs: DC and Switching Characteristics R DS083-3 v2.7 March 24, 2003 Advance Product Specification Virtex-II Pro Electrical Characteristics Virtex-II Pro devices are provided in -7, -6, and -5 speed grades, with -7 having the highest performance.

Contextual Info: S C A N 12 1 00 SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement Texa s In s t r u m e n t s Literature Number: SNLS245D Semiconductor SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and

XC2VP30-FF896

Abstract: LVDCI25 XC2VP7FF896 xc2vp40ff1148 LVDCI33 XC2VP20FF896 Xilinx XC2VP30-FF896 XC2VP100FF1704 XC2VP4FF672 xc2vp70ff1517
Contextual Info: `6 54 Virtex-II Pro Platform FPGAs: DC and Switching Characteristics R DS083-3 v2.11 October 14, 2003 Advance Product Specification Virtex-II Pro Electrical Characteristics Virtex-II Pro devices are provided in -7, -6, and -5 speed grades, with -7 having the highest performance.